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TCM129C18DW Datasheet(PDF) 7 Page - Texas Instruments |
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TCM129C18DW Datasheet(HTML) 7 Page - Texas Instruments |
7 / 17 page TCM29C18, TCM29C19, TCM129C18, TCM129C19 ANALOG INTERFACE FOR DSP SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode (see Figure 5) MIN MAX UNIT td(TSDX) Delay time, time-slot from DCLKX (see Note 10) 140 td(DCLKX)–140 ns td(FSX) Delay time, frame sync 100 tc(CLK)–100 ns tc(DCLKX) Pulse duration, DCLKX 488 15620 ns NOTE 10: tFSLX minimum requirement overrides the td(TSDX) maximum requirement for 64-kHz operation. receive timing requirements over recommended ranges of supply voltages and operating free-air temperature, variable-data-rate mode (see Figure 6) MIN MAX UNIT td(TSDR) Delay time, time slot from DCLKR (see Note 11) 140 tw(DCLKR)–140 ns td(FSR) Delay time, frame sync TC(CLK) 100 tc(CLK)–100 ns tsu(PCM IN) Setup time before bit 7 falling edge 10 ns th(PCM IN) Hold time after bit 8 falling edge 60 ns tw(DCLKR) Pulse duration, DCLKR 488 15620 ns tSER Time-slot end receive time 0 ns NOTE 11: tFSLR minimum requirement overrides the tc(TSDR) maximum requirement for 64-kHz operation. 64 k-bit operation over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode MIN MAX UNIT tFSLX Transmit frame sync, minimum down time FSX = TTL high for remainder of frame 488 ns tFSLR Receive frame sync, minimum down time FSR = TTL high for remainder of frame 1952 ns tw(DCLK) Pulse duration, data clock 10 µs switching characteristics propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode (see timing diagrams) PARAMETER TEST CONDITIONS MIN MAX UNIT tpd1 Delay time from rising edge of transmit clock to bit 1 data valid at PCM OUT (data enable time on time-slot entry) CL = 0 to 100 pF 0 145 ns tpd2 Delay time from rising edge of transmit clock bit n to bit n data valid at PCM OUT (data valid time) CL = 0 to 100 pF 0 145 ns tpd3 Delay time from falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT (data float time on time-slot exit) CL = 0 60 215 ns tpd4 Delay time from rising edge of transmit clock bit 1 to TSX active (low) (time-slot enable time) CL = 0 to 100 pF 0 145 ns tpd5 Delay time from falling edge of transmit clock bit 8 to TSX inactive (high) (time-slot disable time) CL = 0 60 190 ns propagation delay times over recommended ranges of operating conditions, variable-data-rate mode PARAMETER TEST CONDITIONS MIN MAX UNIT tpd6 Delay time from DCLKX 0 100 ns tpd7 Delay time from time-slot enable to PCM OUT CL = 0 to 100 pF 0 50 ns tpd8 Delay time from time-slot disable to PCM OUT 0 80 ns tpd9 Delay time from FSX td(TSDX) = 140 ns 0 140 ns |
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