TCM37C14A, TCM37C15A

PCM COMBO WITH PROGRAMMABLE GAIN CONTROL

SLWS018B – JUNE 1996 – REVISED MAY 1998

8

POST OFFICE BOX 655303

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (outputs not loaded) (unless otherwise noted) (continued)

transmit filter transfer function (see Figure 1)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

Transmit absolute delay time to PCMOUT

fMCLK = 2.048 MHz,

Input to ANLGIN is 1.02 kHz at 0 dBm0

245

µs

f = 500 Hz to 600 Hz

170

Transmit differential envelope delay time

f = 600 Hz to 1000 Hz

95

µs

y

relative to transmit absolute delay time

f = 1000 Hz to 2600 Hz

45

µs

f = 2600 Hz to 2800 Hz

105

Receive absolute delay time to PWRO +

fMCLK = 2.048 MHz, Digital input is digital milliwatt codes

190

µs

f = 500 Hz to 600 Hz

45

Receive differential envelope delay time

f = 600 Hz to 1000 Hz

35

µs

y

relative to transmit absolute delay time

f = 1000 Hz to 2600 Hz

85

µs

f = 2600 Hz to 2800 Hz

110

16.67 Hz

–30

50 Hz

–25

60 Hz

–23

Gain (voltage amplification) relative to gain

Input amplifier set for unity gain,

Noninverting maximum gain output

200 Hz

– 1.8

– 0.125

dB

(g

)

g

at 1.02 kHz

Noninverting maximum gain out ut,

Input signal at ANLGIN is 0 dBm0

300 Hz to 3 kHz

– 0.15

0.15

dB

In ut signal at ANLGIN is 0 dBm0

3.3 kHz

– 0.35

0.15

3.4 kHz

–1

– 0.1

4 kHz

–14

† All typical values are at VBB = –5 V, VCC = 5 V, and TA = 25°C.

receive filter transfer function (see Figure 2)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Below 20 Hz

0.15

20 Hz

0.15

200 Hz

– 0.5

0.15

Gain (voltage amplification) relative to gain at 1 02 kHz

Input signal at PCMIN is 0 dBm0

300 Hz to 3 kHz

– 0.15

0.15

dB

Gain (voltage amplification) relative to gain at 1.02 kHz

Input signal at PCMIN is 0 dBm0

3.3 kHz

– 0.35

0.15

dB

3.4 kHz

–1

– 0.1

4 kHz

–14

4.6 kHz and above

–30

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

MIN

NOM

MAX

UNIT

tc(MCLK)

Clock period, MCLK (2.048 MHz systems)

488

ns

tr

Rise time, MCLK

5

30

ns

tf

Fall time, MCLK

5

30

ns

tw(MCLK) Pulse duration, MCLK (see Note 7)

220

ns

Clock duty cycle [tw(CLK)/tc(CLK)], MCLK

45%

50%

55%

NOTE 7: FSX CLK and FSR CLK must be phase-locked with MCLK.