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THS8133ATQFP Datasheet(PDF) 6 Page - Texas Instruments |
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THS8133ATQFP Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 23 page  THS8133, THS8133A, THS8133B TRIPLE 10-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION SLVS204C – APRIL 1999 – REVISED SEPTEMBER 2000 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 programming example (continued) T0 T1 T2 T3 T4 T5 T6 T7 T8 RPr(0) RPr(1) RPr(2) RPr(3) RPr(4) RPr(5) RPr(6) RPr(7) RPr(8) GY(0) GY(1) GY(2) GY(3) GY(4) GY(5) GY(6) GY(7) GY(8) BPb(0) BPb(1) BPb(2) BPb(3) BPb(4) BPb(5) BPb(6) BPb(7) BPb(8) CLK RPr[9–0] GY[9–0] BPb[9–0] ARPr, AGY, ABPb output corresponding to RPr(0), GY(0), BPb(0) data path latency = 7 CLK cycles RPr(0), GY(0), BPb(0) registered Figure 3. Input Format and Latency YPbPr 4:4:4 and GBR 4:4:4 Modes First registered sample on RPr[9–0] after L- >H on BLANK is interpreted as Pb[9–0] T0 T1 T2 T3 T4 T5 T6 T7 T8 Pb(0) Pr(0) Pb(2) Pr(2) Pb(4) Pr(4) Pb(6) Pr(6) Pb(8) RPr[9–0] ARPr, AGY, ABPb output corresponding to Pr(0), Y(0), Pb(0) data path latency = 8 CLK cycles Pb(0), Y(0) registered T9 Pr(8) Y(0) Y(1) Y(2) Y(3) Y(4) Y(5) Y(6) Y(7) Y(8) GY[9–0] Y(9) BPb[9–0] BLANK Pr(0), Y(1) registered Figure 4. Input Format and Latency YPbPr 4:2:2 2 ×10 Bit Mode |
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