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TLC2943IDB Datasheet(PDF) 1 Page - Texas Instruments |
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TLC2943IDB Datasheet(HTML) 1 Page - Texas Instruments |
1 / 27 page TLC2943 HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK SLAS249 – NOVEMBER 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Dual TLC2933 by Multichip Module (MCM) Technology D Voltage-Controlled Oscillators (VCO) Section – Complete Oscillator Using Only One External Bias Resistor (RBIAS) – Recommended Lock Frequency Range – 37 MHz to 60 MHz (VDD = 3.3 V ± 0.15 V, TA = –20°C to 75 °C) – 43 MHz to 100 MHz (VDD = 5 V ± 0.25 V, TA = –20°C to 75 °C) D Includes a High Speed Edge-Triggered Phase Frequency Detector (PFD) With Internal Charge Pump D Independent VCO, PFD Power-Down Mode description The TLC2943 is a multichip module product that uses two TLC2933 chips. The TLC2933 chip is composed of a voltage-controlled oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range of the VCO is set by an external bias resistor (R BIAS ). The high-speed PFD with internal charge pump detects the phase difference between the reference frequency input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions that can be used as a power-down mode. The high-speed and stable VCO characteristics of the TLC2933 make the TLC2943 suitable for use in dual high-performance phase-locked loop (PLL) systems. AVAILABLE OPTIONS TA PACKAGE TA SMALL OUTLINE (DB) 20 °Cto75°C TLC2943IDB – 20 °C to 75°C TLC2943IDBR (Tape and Reel) Copyright © 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 LOGIC_1 VDD TEST_1 VCO_1 OUT FIN-A_1 FIN-B_1 PFD_1 OUT LOGIC_1 GND GND NC NC NC GND LOGIC_2 VDD TEST_2 VCO_2 OUT FIN-A_2 FIN-B_2 PFD_2 OUT LOGIC_2 GND VCO_1 VDD RBIAS _1 VCOIN_1 VCO_1 GND VCO_1 INHIBIT PFD_1 INHIBIT NC GND NC NC NC GND VCO_2 VDD RBIAS _2 VCOIN_2 VCO_2 GND VCO_2 INHIBIT PFD_2 INHIBIT NC DB PACKAGE (TOP VIEW) |
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