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TLC320AC02CPM Datasheet(PDF) 6 Page - Texas Instruments |
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TLC320AC02CPM Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 84 page  vi List of Illustrations Figure Title Page 1–1 Control Flow Diagram 1–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Functional Sequence for Primary and Secondary Communication 2–5 . . . . . . . . . . . . . 2–2 Timing Sequence 2–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Master and Stand-Alone Functional Sequence 2–16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Slave and Codec Functional Sequence 2–16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 1 IN + and IN – Gain-Control Circuitry 4–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 2 AIC Stand-Alone and Master-Mode Timing 4–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 3 AIC Slave and Codec Emulation Mode 4–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 4 Master or Stand-Alone FS and FSD Timing 4–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 5 Slave FS to FSD Timing 4–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 6 Slave SCLK to FSD Timing 4–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 7 DOUT Enable Timing From Hi-Z 4–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 8 DOUT Delay Timing to Hi-Z 4–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 9 EOC Frame Timing 4–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 10 Master-Slave Frame-Sync Timing After a Delay Has Been Programmed Into the FSD Registers 4–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 – 11 Master and Slave Frame-Sync Sequence with One Slave 4–5 . . . . . . . . . . . . . . . . . . . . 5 – 1 ADC Low-Pass Response 5–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 – 2 ADC Low-Pass Response 5–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 – 3 ADC Group Delay 5–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 – 4 ADC Band-Pass Response 5–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 – 5 ADC Band-Pass Response 5–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 – 6 ADC High-Pass Response 5–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 – 7 ADC Band-Pass Group Delay 5–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 – 8 DAC Low-Pass Response 5–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 – 9 DAC Low-Pass Response 5–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 – 10 DAC Low-PASS Group Delay 5–10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 – 11 DAC (sin x)/x Correction Filter Response 5–11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 – 12 DAC (sin x)/x Correction Filter Response 5–12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 – 13 DAC (sin x)/x Correction Error 5–13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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