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48 or 24 Lines of PC/104 DIGITAL I/O WITH COS 104-DIO-48S & 104-DIO-24S D i g i t a l I / O Chip 82C55A (each supports 24 lines) Number of I/O lines 48 or 24 TTL/CMOS compatible Direction Programmable as inputs or outputs in two groups of 4 and 8 per 82C55A Sink and source current 64mA and 32mA respectively Pullup resistors 10K all input lines with optional pull-downs Change of state detection Port by port selectable on rising and falling edge (COS) Throughput Up to 1 Megabyte per second Power output Re-settable fused +5V at 500mA per 50-pin connector I n t e r r u p t s Number of interrupts 11 Interrupt requests IRQ's 3-7, 9-12, 14, 15 Interrupt sources Counter/timer outputs, external interrupt input, or DIO lines with change of state detection enabled by software C o u n t e r / T i m e r s Chip Type 82C54 Counter/timers 3 x 16 bit Maximum input frequency 10MHz On-board time-base 1MHz Signal type TTL Input voltage Logic low: -0.5V min, 0.8V max; Logic high: 2.0V min, 5.0V max Output voltage Logic low: 0.0V min, 0.4V max; Logic high: 3.0V min, 5.0V max G e n e r a l Power required +5V at 50mA typical, all outputs open Operating temperature 0 to 70°C, optional -40 to +85°C, all versions Storage temperature -50 to 120°C Operating humidity 5% to 95% RH, non-condensing Specifications Block Diagram & Pin Configuration Ordering Guide 104-DIO-48S 48 lines of digital I/O with change of state detection 104-DIO-24S 24 lines of digital I/O with change-of-state detection PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 +5 VDC Port C Hi Port C Hi Port C Hi Port C Hi Port C Lo Port C Lo Port C Lo Port C Lo Port B Port B Port B Port B Port B Port B Port B Port B Port A Port A Port A Port A Port A Port A Port A Port A GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 02 01 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Clock 0 Input Output 0 Gate 1 Input Clock 2 Input Output 2 Gate 0 Input 1MHz Clock (out) Output 1 Gate 2 Input Ground 02 01 03 04 05 06 07 08 09 10 CTR/Timer I/O Header ©Copyright 2006 Advanced Digital Logic, Inc. Specifications subject to change without notice. Advanced Digital Logic, Inc. 4411 Morena Blvd. Suite 101 San Diego, CA 92117 Email: sales@adlogic-pc104.com Website: www.adlogic-pc104.com Tel: (858) 490-0597 Fax: (858) 490-0599 |
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