ADF4150 datasheet(3/27 Pages) AD | Fractional-N/Integer-N PLL Synthesizer

3 page

ADF4150

Rev. 0 | Page 3 of 28

SPECIFICATIONS

AVDD = DVDD = SDVDD = 3.3 V ± 10%; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. The

operating temperature range is −40°C to +85°C.

Table 1.

Parameter

B Version

Unit

Conditions/Comments

Min

Typ

Max

REF

IN CHARACTERISTICS

Input Frequency

250

MHz

For f < 10 MHz ensure slew rate > 21 V/µs

Input Sensitivity

0.7

V p-p

Biased at AV

DD/2

Input Capacitance

5.0

Input Current

±60

µA

RF INPUT CHARACTERISTICS

RF Input Frequency (RF

IN), RF Output

Buffer Disabled

0.5

4.0

GHz

−10 dBm ≤ RF input power ≤ +5 dBm

RF Input Frequency (RF

IN), RF Output

Buffer Disabled

0.5

5.0

GHz

−5 dBm ≤ RF input power ≤ +5 dBm

RF Input Frequency (RF

IN) RF Output

Buffer Enabled

0.5

3.5

GHz

−10 dBm ≤ RF input power ≤ +5 dBm

RF Input Frequency (RF

IN) RF Output

Buffer and Dividers Enabled

0.5

3.0

GHz

−10 dBm ≤ RF input power ≤ +5 dBm

Prescaler Output Frequency

750

MHz

MAXIMUM PFD FREQUENCY

Fractional-N (Low Spur Mode)

MHz

Fractional-N Mode (Low Noise Mode)

MHz

Integer-N Mode

MHz

CHARGE PUMP

CP Sink/Source

SET = 5.1 kΩ

High Value

4.65

Low Value

0.29

SET Range

2.7

kΩ

CP Leakage

CP = VP/2

Sink and Source Current Matching

0.5 V ≤ V

CP ≤ VP − 0.5 V

CP vs. VCP

0.5 V ≤ V

CP ≤ VP − 0.5 V

CP vs. Temperature

CP = VP/2

LOGIC INPUTS

Input High Voltage, V

INH

1.5

Input Low Voltage, V

INL

0.6

Input Current, I

INH/IINL

±1

µA

Input Capacitance, C

3.0

LOGIC OUTPUTS

Output High Voltage, V

DD − 0.4

CMOS output chosen

Output High Current, I

500

µA

Output Low Voltage, V

0.4

OL = 500 µA

POWER SUPPLIES

3.0

3.6

DD, SDVDD

5.5

DD + AIDD

Output Dividers

6 to 24

Each output divide by two consumes 6 mA

RFOUT

RF output stage is programmable

Low Power Sleep Mode

µA

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