TLC548C, TLC548I, TLC549C, TLC549I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996

8

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

The TLC548 and TLC549 are each complete data acquisition systems on a single chip. Each contains an internal

system clock, sample-and-hold function, 8-bit A/D converter, data register, and control logic circuitry. For flexibility

and access speed, there are two control inputs: I/O CLOCK and chip select (CS). These control inputs and a

TTL-compatible 3-state output facilitate serial communications with a microprocessor or minicomputer. A conversion

can be completed in 17

µs or less, while complete input-conversion-output cycles can be repeated in 22 µs for the

TLC548 and in 25

µs for the TLC549.

The internal system clock and I/O CLOCK are used independently and do not require any special speed or phase

relationships between them. This independence simplifies the hardware and software control tasks for the device.

Due to this independence and the internal generation of the system clock, the control hardware and software need

only be concerned with reading the previous conversion result and starting the conversion by using the I/O clock. In

this manner, the internal system clock drives the “conversion crunching” circuitry so that the control hardware and

software need not be concerned with this task.

When CS is high, DATA OUT is in a high-impedance condition and I/O CLOCK is disabled. This CS control function

allows I/O CLOCK to share the same control logic point with its counterpart terminal when additional TLC548 and

TLC549 devices are used. This also serves to minimize the required control logic terminals when using multiple

TLC548 and TLC549 devices.

The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain

the conversion result. A normal control sequence is:

1.

CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges

and then a falling edge of the internal system clock after a CS

↓ before the transition is recognized. However,

technique protects the device against noise when used in a noisy environment. The most significant bit (MSB)

of the previous conversion result initially appears on DATA OUT when CS goes low.

2.

The falling edges of the first four I/O CLOCK cycles shift out the second, third, fourth, and fifth most significant

bits of the previous conversion result. The on-chip sample-and-hold function begins sampling the analog

input after the fourth high-to-low transition of I/O CLOCK. The sampling operation basically involves the

charging of internal capacitors to the level of the analog input voltage.

3.

Three more I/O CLOCK cycles are then applied to the I/O CLOCK terminal and the sixth, seventh, and eighth

conversion bits are shifted out on the falling edges of these clock cycles.

4.

The final (the eighth) clock cycle is applied to I/O CLOCK. The on-chip sample-and-hold function begins the

hold operation upon the high-to-low transition of this clock cycle. The hold function continues for the next four

internal system clock cycles, after which the holding function terminates and the conversion is performed

during the next 32 system clock cycles, giving a total of 36 cycles. After the eighth I/O CLOCK cycle, CS must

go high or the I/O clock must remain low for at least 36 internal system clock cycles to allow for the completion

of the hold and conversion functions. CS can be kept low during periods of multiple conversion. When

keeping CS low during periods of multiple conversion, special care must be exercised to prevent noise

glitches on the I/O CLOCK line. If glitches occur on I/O CLOCK, the I/O sequence between the

microprocessor/controller and the device loses synchronization. When CS is taken high, it must remain high

until the end of conversion. Otherwise, a valid high-to-low transition of CS causes a reset condition, which

aborts the conversion in progress.

A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through

4 before the 36 internal system clock cycles occur. Such action yields the conversion result of the previous conversion

and not the ongoing conversion.