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TLC5540INSR Datasheet(PDF) 10 Page - Texas Instruments |
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TLC5540INSR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 18 page TLC5540 SLAS105D − JANUARY 1995 − REVISED APRIL 2004 www.ti.com 10 APPLICATION INFORMATION grounding and power supply considerations A signal ground is a low-impedance path for current to return to the source. Inside the TLC5540 A/D converter, the analog ground and digital ground are connected to each other through the substrate, which has a very small resistance (~30 Ω) to prevent internal latch-up. For this reason, it is strongly recommended that a printed circuit board (PCB) of at least 4 layers be used with the TLC5540 and the converter DGND and AGND pins be connected directly to the analog ground plane to avoid a ground loop. Figure 11 shows the recommended decoupling and grounding scheme for laying out a multilayer PC board with the TLC5540. This scheme ensures that the impedance connection between AGND and DGND is minimized so that their potential difference is negligible and noise source caused by digital switching current is eliminated. 0.1 µF 0.1 µF 11 13 24 2 14 15 18 20 21 VDDD GND VDDA AGND TLC5540 Signal Plane Analog Ground Plane Analog Supply Plane Signal Plane Digital Supply Plane 0.1 µF 0.1 µF 0.1 µF Figure 11. AVDD, DVDD, AGND, and DGND Connections printed circuit board (PCB) layout considerations When designing a circuit that includes high-speed digital and precision analog signals such as a high speed ADC, PCB layout is a key component to achieving the desired performance. The following recommendations should be considered during the prototyping and PCB design phase: D Separate analog and digital circuitry physically to help eliminate capacitive coupling and crosstalk. When separate analog and digital ground planes are used, the digital ground and power planes should be several layers from the analog signals and power plane to avoid capacitive coupling. D Full ground planes should be used. Do not use individual etches to return analog and digital currents or partial ground planes. For prototyping, breadboards should be constructed with copper clad boards to maximize ground plane. D The conversion clock, CLK, should be terminated properly to reduce overshoot and ringing. Any jitter on the conversion clock degrades ADC performance. A high-speed CMOS buffer such as a 74ACT04 or 74AC04 positioned close to the CLK terminal can improve performance. D Minimize all etch runs as much as possible by placing components very close together. It also proves beneficial to place the ADC in a corner of the PCB nearest to the I/O connector analog terminals. D It is recommended to place the digital output data latch (if used) as close to the TLC5540 as possible to minimize capacitive loading. If D0 through D7 must drive large capacitive loads, internal ADC noise may be experienced. |
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