TLC5910

LED DRIVER

SLLS392 – NOVEMBER 1999

6

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

BCENA

94

I

Brightness control enable. When BCENA is low, brightness control latch is set to the default

value. The output current value in this status is 100% of setting the value by an external resistor.

The frequency division ratio of GSCLK is 1/1. When BCENA is high, writing to brightness control

latch is enabled.

BLANK

67

I

Blank(light off). When BLANK is high, all outputs of the constant current driver are turned off.

When GSPOL is high, the output is turned on (LED on), synchronizing to the falling edge of

GSCLK after the next rising edge of GSCLK, when BLANK goes from high to low. When GSPOL

is low, the output is turned on (LED on), synchronizing to the rising edge of GSCLK after the

next falling edge of GSCLK, when BLANK goes from high to low.

BOUT

53

O

BLANK buffered output

DCCLK

62

I

Clock input for data transfer. The input data is from DCDIN (port B) , output data at DCDOUT,

and all data on the shift register for dot correction data, from DCDIN, is shifted by 1 bit

synchronizing to the rising edge of DCCLK.

DCDIN0 –

DCDIN5

86,87,88,

89,90,91

I

Input for 6 bit parallel data (port B). These terminals are used as a shift register input for dot

correction data.

DCDOUT0 –

DCDOUT5

40,39,38,

37,36,35

O

Output for 6 bit parallel data (port B). These terminals are used as a shift register output for dot

correction data.

DCENA

95

I

Latch enable for dot correction data. When DCENA is low, the latch is set to the default value.

At this time, the output current value is 100% of the value set by an external resistor.

DCLK

64

I

Clock input for data transfer. The input data is from DIN (port A) , all data on the shift register

selected by RSEL, 1 and output data at DOUT is shifted by 1 bit synchronizing to DCLK. Note

that synchronizing to either the rising or falling edge of DCLK depends on the value of DPOL.

DIN0 – DIN9

76,77,78,79,80,

81,82,83,84,85

I

Input for 10 bit parallel data (port A). These terminals are inputs to the shift register for gray scale

data, brightness control, and dot correction data. The register selected is determined by RSEL0,

1.

DOUT0 –

DOUT9

50,49,48,47,46,

45,44,43,42,41

O

Output for 10 bit parallel data (port A). These terminals are outputs to the shift register for gray

scale data, brightness control, and dot correction data. The register selected is determined by

RSEL0, 1.

DPOL

96

I

Select the valid edge of DCLK. When DPOL is high, the rising edge of DCLK is valid. When

DPOL is low, the falling edge of DCLK is valid.

GNDANA

28

Analog ground (internally connected to GNDLOG and GNDLED)

GNDLOG

98

Logic ground (internally connected to GNDANA and GNDLED)

GNDLED

1,4,7,10,13,

16,19,22,25

LED driver ground (internally connected to GNDANA and GNDLED)

GSCLK

68

I

Clock input for gray scale. When MAG0 to MAG2 are all low, GSCLK is used for pulse width

control, and GSCLK is used for PLL timing control when either MAG is not low. The gray scale

display is accomplished by lighting LEDs on until the number of GSCLK or PLL clocks counted

is equal to data latched.

GSPOL

69

I

Select the valid edge of GSCLK. When GSPOL is high, the rising edge of GSCLK is valid. When

GSPOL is low, the falling edge of GSCLK is valid.

IREF

32

I/O

Constant current value setting. LED current is set to the desired value by connecting an external

resistor between IREF and GND. The 38 times current compares current across the external

resistor sink on the output terminal.

LEDCHK

58

I

LED disconnection detection enable. When LEDCHK is high, LED disconnection detection is

enabled and XDOWN2 is valid. When LEDCHK is low, LED disconnection detection is disabled.

MAG0 – MAG2

73,72,71

I

PLL multiple ratio setting. The clock frequency generated by PLL referenced to GSCLK is set.

OPEN

57

TEST. Factory test terminal. OPEN should be opened.