TLC5628C, TLC5628I

OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

7

POST OFFICE BOX 655303

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level input current

VI = VDD

±10

µA

IIL

Low-level input current

VI = 0 V

±10

µA

IO(sink)

Output sink current

Each DAC output

20

µA

IO(source)

Output source current

Each DAC output

2

mA

Ci

Input capacitance

15

pF

Ci

Reference input capacitance

15

pF

IDD

Supply current

VDD = 5 V

4

mA

Iref

Reference input current

VDD = 5 V,

Vref = 2 V

±10

µA

EL

Linearity error (end point corrected)

Vref = 2 V,

× 2 gain (see Note 1)

±1

LSB

ED

Differential-linearity error

Vref = 2 V,

× 2 gain (see Note 2)

±0.9

LSB

EZS

Zero-scale error

Vref = 2 V,

× 2 gain (see Note 3)

0

30

mV

Zero-scale-error temperature coefficient

Vref = 2 V,

× 2 gain (see Note 4)

10

µV/°C

EFS

Full-scale error

Vref = 2 V,

× 2 gain (see Note 5)

±60

mV

Full-scale-error temperature coefficient

Vref = 2 V,

× 2 gain (see Note 6)

±25

µV/°C

PSRR

Power supply rejection ratio

See Notes 7 and 8

0.5

mV/V

NOTES:

1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects

of zero code and full-scale errors).

2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.

Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

4. Zero-scale-error temperature coefficient is given by: ZSETC = [ZSE(Tmax) – ZSE(Tmin)]/Vref × 106/(Tmax – Tmin).

5. Full-scale error is the deviation from the ideal full-scale output (Vref – 1 LSB) with an output load of 10 kΩ.

6. Full-scale error temperature coefficient is given by: FSETC = [FSE(Tmax) – FSE (Tmin)]/Vref × 106/(Tmax – Tmin).

7. Zero-scale-error rejection ratio (ZSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of

this signal imposed on the zero-code output voltage.

8. Full-scale-error rejection ratio (FSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of

this signal imposed on the full-scale output voltage.

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output slew rate

CL = 100 pF,

RL = 10 kΩ

1

V/

µs

Output settling time

To

±0.5 LSB,

CL = 100 pF, RL = 10 kΩ,

See Note 9

10

µs

Large signal bandwidth

Measured at – 3 dB point

100

kHz

Digital crosstalk

CLK = 1-MHz square wave measured at DACA-DACD

–50

dB

Reference feedthrough

See Note 10

–60

dB

Channel-to-channel isolation

See Note 11

–60

dB

Reference input bandwidth

See Note 12

100

kHz

NOTES:

9. Settling time is the time between a LOAD falling edge and the DAC output reaching full-scale voltage within

±0.5 LSB starting from

an initial output voltage equal to zero.

10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 Vpp at 10 kHz.

11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex

with Vref input = 1 V dc + 1 Vpp at 10 kHz.

12. Reference bandwidth is the –3 dB bandwidth with an input at Vref = 1.25 V dc + 2 Vpp and with a full-scale digital input code.