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TLV1562IPW Datasheet(PDF) 2 Page - Texas Instruments |
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TLV1562IPW Datasheet(HTML) 2 Page - Texas Instruments |
2 / 40 page TLV1562 2.7 V TO 5.5 V, HIGH-SPEED LOW-POWER RECONFIGURABLE ANALOG-TO-DIGITAL CONVERTER WITH 4-INPUT, DUAL S/H, PARALLEL INTERFACE, AND POWER DOWN SLAS162 – SEPTEMBER 1998 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram REF M U X S/H 4/8/10-Bit Recyclic ADC OSC (7.5 MHz Min) Serial/Parallel Conv and FIFO 3-State Buffer Control Register Interface Timing and Control AVDD DVDD BDVDD AGND DGND BDGND AP/CH1 D (0–9) CS/OE INT CSTART WR SysClk AM/CH2 BP/CH3 BM/CH4 VREFP VREFM CLKIN RD (15 MHz Max) VREFMID S/H Amplifier description The TLV1562 is a 10-bit CMOS low-power, high-speed programmable resolution analog-to-digital converter based on a low-power recyclic architecture. The unique architecture delivers a throughput up to 2 MSPS (million samples per second) at 10-bit resolution. The programmable resolution allows a higher conversion throughput as a tradeoff of lower resolution. A high speed 3-state parallel port directly interfaces to a digital signal processor (DSP) or microprocessor ( µP) system data bus. D0 through D9 are the digital output terminals with D0 being the least significant bit (LSB). The TLV1562 is designed to operate for a wide range of supply voltages (2.7 V to 5.5 V) with very low power consumption (11 mA maximum at 5.5 V, 10 MHz CLKIN). The power saving feature is further enhanced with a software power-down feature (1 µA maximum) and auto power-down (1 µA maximum) feature. Many programmable features make this device a flexible general-purpose data converter. The device can be configured as either four single-ended inputs to maximize the capacity or two differential inputs to improve noise immunity. The internal system clock (SYSCLK) may come from either an internally generated OSC or an external clock source (CLKIN). Four different modes of conversion are available for different applications. The interrupt driven modes are mostly suitable for asynchronous applications, while the continuous modes take advantage of the high speed nature of a pipelined architecture. A pair of built-in sample-and-hold amplifiers allow simultaneous sampling of two input channels. This makes the TLV1562 perfect for communication applications. Conversion is started by the RD signal, which can also be used for reading data, to maximize the throughput. Conversion can be started either by the RD or CSTART signal when the device is operating in the interrupt-driven modes. The dedicated conversion start pin, CSTART, provides a mechanism to simultaneously sample and convert multiple channels when multiple converters are used in an application. |
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