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TLV2545IDGK Datasheet(PDF) 4 Page - Texas Instruments |
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TLV2545IDGK Datasheet(HTML) 4 Page - Texas Instruments |
4 / 26 page TLV2541, TLV2542, TLV2545 2.7 V TO 5.5 V, LOW POWER, 12-BIT, 200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245 –MARCH 2000 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description (continued) GND/AIN(–) ADC Code AIN Charge Redistribution DAC Control Logic _ + Figure 1. Simplified SAR Circuit serial interface OUTPUT DATA FORMAT MSB LSB D15–D4 D3–D0 Conversion result (OD11–OD0) Don’t care The output data format is binary (unipolar straight binary). binary Zero scale code = 000h, Vcode = GND Full scale code = FFFh, Vcode = VREFP – 1 LSB pseudo-differential inputs The TLV2545 operates in pseudo-differential mode. The inverted input is available on pin 5. It can have a maximum input ripple of ±0.2 V. This is normally used for ground noise rejection. control and timing start of the cycle TLV2541 D When FS is not used ( FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle. Output data changes on the rising edge of SCLK. This is typically used for a microcontroller with SPI interface, although it can also be used for a DSP. The microcontroller SPI interface should be programmed for CPOL=0 (serial clock referenced to ground) and CPHA=1 (data is valid on the falling edge of serial clock). D When FS is used ( FS is an active signal from a DSP), the falling edge of FS is the start of the cycle. Output data changes on the rising edge of SCLK. This is typically used for a TMS320 DSP. If the TLV2541 is attached to a dedicated DSP serial port. CS terminal can be grounded. TLV2542/5 The CS and FS inputs are accessed via the same pin (pin 1) on the TLV2542 and TLV2545. The cycle is started by the falling edge transition provided by either a CS (interfacing with SPI microcontroller) signal or FS (interfacing with TMS320 DSP) signal. Timing for the TLV2545 is much like the TLV2541, with the exception of the CS/FS line. |
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