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TLV5580PW Datasheet(PDF) 7 Page - Texas Instruments |
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TLV5580PW Datasheet(HTML) 7 Page - Texas Instruments |
7 / 34 page TLV5580 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions with fCLK = 80 MSPS and use of external voltage references (unless otherwise noted) dc accuracy PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Integral nonlinearity (INL) best fit Internal references (see Note 1) TA = 25°C –2 ±1 2 LSB Integral nonlinearity (INL), best-fit Internal references (see Note 1) TA = –40°C to 85°C –2.4 ±1 2.4 LSB Differential nonlinearity (DNL) Internal references (see Note 2), TA = –40°C to 85°C –1 ±0.6 1.3 LSB Zero error AVDD =DVDD =3 3V DRVDD =3V See Note 3 5 %FS Full scale error AVDD = DVDD = 3.3 V, DRVDD = 3 V See Note 3 5 %FS NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full–scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two endpoints. 2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last transition level – first transition level) ÷ (2n – 2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than –1 LSB ensures no missing codes. 3. Zero error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (256). Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (256). analog input PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CI Input capacitance 4 pF reference input (AVDD = DVDD = DRVDD = 3.6 V) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Rref Reference input resistance 200 Ω Iref Reference input current 5 mA reference outputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(REFTO) Reference top offset voltage Absolute min/max values valid 2.07 2 + [(AVDD – 3) ÷ 2] 2.21 V V(REFBO) Reference bottom offset voltage and tested for AVDD = 3.3 V 1.09 1 + [(AVDD – 3) ÷ 2] 1.21 V |
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