TLV5606

2.7V TO 5.5V LOW POWER 10BIT DIGITALTOANALOG

CONVERTERS WITH POWER DOWN

SLAS259B − DECEMBER 1999 − REVISED APRIL 2004

3

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7 V

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Reference input voltage range

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Digital input voltage range

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0

°C to 70°C

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TLV5606I

−40

°C to 85°C

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−65

°C to 150°C

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Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

°C

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† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, VDD

VDD = 5 V

4.5

5

5.5

V

Supply voltage, VDD

VDD = 3 V

2.7

3

3.3

V

High-level digital input voltage, VIH

DVDD = 2.7 V

2

V

High-level digital input voltage, VIH

DVDD = 5.5 V

2.4

V

Low-level digital input voltage, VIL

DVDD = 2.7 V

0.6

V

Low-level digital input voltage, VIL

DVDD = 5.5 V

1

V

Reference voltage, Vref to REFIN terminal

VDD = 5 V (see Note 1)

AGND

2.048

VDD −1.5

V

Reference voltage, Vref to REFIN terminal

VDD = 3 V (see Note 1)

AGND

1.024

VDD −1.5

V

Load resistance, RL

2

10

k

Ω

Load capacitance, CL

100

pF

Clock frequency, fCLK

20

MHz

Operating free-air temperature, TA

TLV5606C

0

70

°C

Operating free-air temperature, TA

TLV5606I

−40

85

°C

NOTE 1: Due to the x2 output buffer, a reference input voltage

≥ VDD/2 causes clipping of the transfer function.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

power supply

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD = 5 V, VREF = 2.048 V,

No load,

Fast

0.9

1.35

mA

IDD

Power supply current

No load,

All inputs = AGND or VDD,

DAC latch = 0x800

Slow

0.4

0.6

mA

IDD

Power supply current

VDD = 3 V, VREF = 1.024 V

No load,

Fast

0.7

1.1

mA

No load,

All inputs = AGND or VDD,

DAC latch = 0x800

Slow

0.3

0.45

mA

Power down supply current (see Figure 12)

10

nA

PSRR

Power supply rejection ratio

Zero scale

See Note 2

−80

dB

PSRR

Power supply rejection ratio

Full scale

See Note 3

−80

dB

Power on threshold voltage, POR

2

V

NOTES:

2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) − EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:

PSRR = 20 log [(EG(VDDmax) − EG(VDDmin))/VDDmax]