TLV5619

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER

WITH POWER DOWN

SLAS172C – DECEMBER 1997 – REVISED APRIL 2000

2

POST OFFICE BOX 655303

functional block diagram

_

+

REFIN

12

19

20

1

2

3

4

5

6

18

17

D0

D1

D2

D3

D4

D5

D6

D7

CS

WE

Power-On

Reset

12

12

x2

LDAC

16

13

OUT

12-Bit

Input

Register

Select

and

Control

Logic

12-Bit

DAC

Latch

7

D8

8

D9

9

D10

10

D11

PD

15

Resistor

String DAC

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

CS

18

I

Chip select

D0 (LSB)–D11 (MSB)

19, 20,

1 – 10

I

Parallel data input

GND

14

Ground

LDAC

16

I

Load DAC

OUT

13

O

Analog output

PD

15

I

When low, disables all buffer amplifier voltages to reduce supply current

REFIN

12

I

Voltage reference input

VDD

11

Positive power supply

WE

17

I

Write enable