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TLV5614IPWR Datasheet(PDF) 7 Page - Texas Instruments |
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TLV5614IPWR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 27 page TLV5614 2.7-V TO 5.5-V 12-BIT 3- µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS188 – SEPTEMBER 1998 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) (continued) digital input timing requirements MIN NOM MAX UNIT tsu(CS–FS) Setup time, CS low before FS ↓ 10 ns tsu(FS–CK) Setup time, FS low before first negative SCLK edge 8 ns tsu(C16–FS) Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising edge of FS 10 ns tsu(C16–CS) Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and CS rising edge. 10 ns twH Pulse duration, SCLK high 25 ns twL Pulse duration, SCLK low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 8 ns th(D) Hold time, data held valid after SCLK falling edge 5 ns twH(FS) Pulse duration, FS high 20 ns PARAMETER MEASUREMENT INFORMATION 12 3 4 5 15 16 D15 D14 D13 D12 D1 D0 tsu(FS-CK) tsu(CS-FS) twH(FS) th(D) tsu(D) twH twL tsu(C16-CS) tsu(C16-FS) SCLK DIN CS FS Figure 1. Timing Diagram |
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