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TLV986PFB Datasheet(PDF) 6 Page - Texas Instruments |
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TLV986PFB Datasheet(HTML) 6 Page - Texas Instruments |
6 / 20 page TLV986 3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR SLAS228 – JULY 1999 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range, TA = 25°C, AVDD = DVDD = 3 V, ADCCLK = 12.5 MHz (unlessotherwise noted) (continued) reference voltages PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Internal bandgap voltage reference 1.43 1.50 1.58 V Temperature coefficient 100 ppm/ °C ADC Reference+ Externally decoupled 1.8 2 2.2 V ADC Reference– Externally decoupled 0.9 1 1.1 V digital specifications logic inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level input current DIVDD =3V –10 10 µA IIL Low-level input current DIVDD = 3 V –10 10 µA Ci Input capacitance 5 pF logic outputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage IOH = 50 µA, DIVDD = 3 V DIVDD–0.4 V VOL Low-level output voltage IOL= 50 µA, DIVDD = 3 V 0.4 V IOZ High-impedance-state output current –10 10 µA CO Output capacitance 5 pF key timing requirements PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(SRW) SR pulse width Measured at 50% of pulse height 10 ns t(SVW) SV pulse width Measured at 50% of pulse height 10 ns t(OBS) OBCLP falling edge to ADCCLK rising edge Minimum 0.25 × one ADCCLK cycle t(OBE) ADCCLK falling edge to OBCLP rising edge Not critical, but should not exceed 2N pixels t(OD) ADCCLK to output data delay 4 9 ns t(CSF) CS falling edge to SCLK rising edge 0 ns t(CSR) SCLK falling edge to CS rising edge 5 ns 0 5 10 15 20 25 30 35 40 0 28 56 84 112 140 168 196 224 252 280 308 336 364 392 420 448 476 504 PGA – Gain Code TLV986 GAIN |
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