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TMS320F241FN Datasheet(PDF) 6 Page - Texas Instruments |
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TMS320F241FN Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 66 page  TMS320C242 DSP CONTROLLER SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Terminal Functions - ’C242 PG and FN Packages NAME 64-PIN QFP 68-PIN PLCC TYPE† RESET STATE‡ DESCRIPTION NAME NO. NO. TYPE† STATE‡ DESCRIPTION INTERFACE CONTROL SIGNALS WDDIS 52 63 I I Watchdog disable. Note that on ROM devices, only the WDDIS function is valid. If the input is low, the watchdog timer cannot be disabled in the software. If the input is high, the watchdog timer can be disabled in the software through the WDDIS bit in the WDCR register. ANALOG-TO-DIGITAL CONVERTER (ADC) INPUTS ADCIN00 24 32 ADCIN01 23 31 ADCIN02 22 30 ADCIN03 21 29 I I Analog inputs to the ADC ADCIN04 20 28 I I Analog inputs to the ADC ADCIN05 19 26 ADCIN06 18 25 ADCIN07 15 22 VCCA 14 21 – – Analog supply voltage for ADC (5 V). VCCA must be isolated from digital supply voltage. VSSA 13 20 – – Analog ground reference for ADC VREFHI 16 23 – – ADC analog high-voltage reference input VREFLO 17 24 – – ADC analog low-voltage reference input EVENT MANAGER T1CMP/T1PWM/ IOPB4 12 19 I/O/Z Timer 1 compare output/general-purpose bidirectional digital I/O (GPIO). T2CMP/T2PWM/ IOPB5 11 18 I/O/Z Timer 2 compare output/GPIO TDIR/ IOPB6 56 67 I/O Counting direction for GP timer/GPIO. If TDIR=1, upward counting is selected. If TDIR=0, downward counting is selected. TCLKIN/ IOPB7 57 68 I/O External clock input for GP timer/GPIO. Note that timer can also use the internal device clock. CAP1/QEP0/ IOPA3 8 15 I/O Capture input #1/quadrature encoder pulse input #0/GPIO CAP2/QEP1/ IOPA4 7 14 I/O I Capture input #2/quadrature encoder pulse input #1/GPIO CAP3/ IOPA5 6 13 I/O I Capture input #3/GPIO PWM1/ IOPA6 64 7 I/O/Z Compare/PWM output pin #1 or GPIO PWM2/ IOPA7 63 6 I/O/Z Compare/PWM output pin #2 or GPIO PWM3/ IOPB0 62 5 I/O/Z Compare/PWM output pin #3 or GPIO PWM4/ IOPB1 61 4 I/O/Z Compare/PWM output pin #4 or GPIO PWM5/ IOPB2 60 3 I/O/Z Compare/PWM output pin #5 or GPIO PWM6/IOPB3 59 2 I/O/Z Compare/PWM output pin #6 or GPIO PDPINT 58 1 I I Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins in the high-impedance state, should motor drive/power converter abnormalities, such as overvoltage or overcurrent, etc., arise. PDPINT is a falling-edge-sensitive interrupt. After the falling edge, this pin must be held low for two clock cycles for the core to recognize the interrupt. † I = input, O = output, Z = high impedance ‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is an output, its level at reset is indicated. § These pins are internally pulled high. However, these pins are not pulled high in the emulation devices (’F243/’F241). NOTE: Bold, italicized pin names indicate pin function after reset. |
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