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TMS320LC549 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320LC549 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 61 page TMS320LC549 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS077B – SEPTEMBER 1998 – REVISED FEBRUARY 2000 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Table of Contents Description 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Descriptions 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings 11 . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions 11 . . . . . . . . . . . Timing Parameter Symbology 12 . . . . . . . . . . . . . . . . . . Electrical Characteristics 13 . . . . . . . . . . . . . . . . . . . . . . Divide-by-Two/Divide-by-Four Clock Option 15 . . . . . . Multiply-by-N Clock Option 17 . . . . . . . . . . . . . . . . . . . . . Memory and Parallel I/O Interface Timing 19 . . . . . . . . Timing Requirements for a Memory Read 20 . . . . . . . I/O Timing Variation: SPICE Simulation 27 . . . . . . . . . . Timing For Externally Generated Wait States 30 . . . . . HOLD and HOLDA Timings 35 . . . . . . . . . . . . . . . . . . . . Reset, BIO, Interrupt, and MP/MC Timings 37 . . . . . . . Serial Port Receive Timing 41 . . . . . . . . . . . . . . . . . . . . . Serial Port Transmit Timing 42 . . . . . . . . . . . . . . . . . . . . Buffered Serial Port Receive Timing 44 . . . . . . . . . . . . . Buffered Serial Port Transmit Timing 45 . . . . . . . . . . . . Serial-Port Receive Timing in TDM Mode 48 . . . . . . . . Serial-Port Transmit Timing in TDM Mode 50 . . . . . . . . Host-Port Interface Timing 52 . . . . . . . . . . . . . . . . . . . . . Mechanical Data 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . description The TMS320LC549 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’549) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. The processor also provides an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The ’549 also utilizes a highly specialized instruction set, which is the basis of its operational flexibility and speed. Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the ’549 includes the control mechanisms to manage interrupts, repeated operations, and function calls. This data sheet contains the pin layouts, signal descriptions, and electrical specifications for the TMS320VC549 DSP. For additional information, see the TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital Signal Processors data sheet (literature number SPRS039). The SPRS039 is considered a family functional overview and should be used in conjunction with this data sheet. |
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