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TMS320LF2407PGE Datasheet(PDF) 11 Page - Texas Instruments |
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TMS320LF2407PGE Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 106 page  TMS320LF2407, TMS320LF2406, TMS320LF2402 TMS320LC2406, TMS320LC2404, TMS320LC2402 DSP CONTROLLERS SPRS094C – APRIL 1999 – REVISED OCTOBER 1999 11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 pin functions (continued) Table 2. ’LF240x and ’LC240x Pin List and Package Options†‡ (Continued) PIN NAME ’LF2407 ’2406 ’LC2404 ’2402 DESCRIPTION OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS (CONTINUED) VCCP (5V) 58 40 40 60§ Flash programming voltage pin. This is the 5-V supply used for flash programming. Flash cannot be programmed if this pin is held at 0 V. Connect to 5-V supply for programming or tie it to GND during functional mode. TP1 (Flash) 60 42 42 61§ Flash array test pin. Do not connect. TP2 (Flash) 63 44 44 62§ Flash array test pin . Do not connect. IOPF6 131 92 92 General-purpose I/O ( ↑) BIO/IOPC1 119 85 85 Branch control input. BIO is polled by the BCND pma,BIO instruction. If BIO is low, a branch is executed. If BIO is not used, it should be pulled high. This pin is configured as a branch control input by all device resets. It can be used as a GPIO, if not used as a branch control input. ( ↑) EMULATION AND TEST EMU0 90 61 61 7 Emulator I/O #0 with internal pullup. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. ( ↑) EMU1/OFF 91 62 62 8 Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as an input/output through the JTAG scan. When TRST is driven low, this pin is configured as OFF. EMU1/OFF, when active low, puts all output drivers in the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply: TRST = 0 EMU0 = 1 EMU1/OFF = 0 TCK 135 94 94 29 JTAG test clock with internal pullup ( ↑) TDI 139 96 96 30 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. ( ↑) TDO 142 99 99 31 JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK. ( ↓) TMS 144 100 100 32 JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. ( ↑) TMS2 36 25 25 48 JTAG test-mode select 2 (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. Used for test and emulation only. ( ↑) TRST 1 1 1 33 JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. ( ↓) † Bold, italicized pin names indicate pin function after reset. ‡ GPIO – General-purpose input/output pin. All GPIOs come up as input after reset. § Pin changes with respect to SPRS094B data sheet. LEGEND: ↑ – Internal pullup ↓ – Internal pulldown |
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