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TMS370C020A Datasheet(PDF) 6 Page - Texas Instruments |
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TMS370C020A Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 60 page  TMS370Cx2x 8-BIT MICROCONTROLLER SPNS018C – FEBRUARY 1993 – REVISED FEBRUARY 1997 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 central processing unit (CPU) The TMS370Cx2x device uses the high-performance 8-bit TMS370 CPU module. The ’x2x uses an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x2x instruction map is shown in Table 17 in the instruction set overview section. The ’370Cx2x CPU architecture provides the following components: D CPU registers: – A stack pointer that points to the last entry in the memory stack – A status register that monitors the operation of the instructions and contains the global interrupt-enable bits – A program counter that points to the memory location of the next instruction to be executed D Memory blocks: – 256-byte general-purpose RAM that can be used for data memory storage, program instructions, general purpose register, or the stack – A peripheral file that provides access to all internal peripheral modules, system-wide control functions, and EEPROM / EPROM programming control – 256-byte EEPROM module, that provides in-circuit programmability and data retention in power-off conditions – 4K- or 8K-byte ROM or 8K-byte EPROM Figure 1 illustrates the CPU registers and memory blocks. |
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