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TMS370CXCXFZ Datasheet(PDF) 11 Page - Texas Instruments |
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TMS370CXCXFZ Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 63 page  TMS370CxCx 8-BIT MICROCONTROLLER SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997 11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 interrupts (continued) TIMER 1 CPU NMI Logic Enable IE1 IE2 Level 1 INT Level 2 INT T1 PRI Priority Overflow Compare 1 Ext Edge Compare 2 Input Capture 1 Watchdog ADC2 INT A / D PRI A/D STATUS REG EXT INT 1 INT1 PRI INT1 SCI2 INT RX BRKDT RXRDY TX TXRDY TXPRI RXPRI Figure 4. Interrupt Control Each system interrupt is configured independently to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is selectively configured on either the high- or low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending-interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions. The TMS370CxCx has five hardware system interrupts (plus RESET) as shown in Table 7. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt may have multiple interrupt sources (for example, SCI RXINT has two interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the associated peripheral file. Each interrupt source FLAG bit is readable individually for software polling or for determining which interrupt source generated the associated system interrupt. Four of the system interrupts are generated by on-chip peripheral functions, and one external interrupt is supported. Software configuration of the external interrupts is performed through the INT1 control register in peripheral file frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual- |
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