TPA0152

2-W STEREO AUDIO POWER AMPLIFIER

WITH DIGITAL VOLUME CONTROL

SLOS246B – JUNE 1999 – REVISED MARCH 2000

3

POST OFFICE BOX 655303

AVAILABLE OPTIONS

PACKAGED DEVICE

TA

TSSOP†

(PWP)

–40

°C to 85°C

TPA0152PWP

† The PWP package is available taped and reeled. To order a taped and reeled part,

add the suffix R to the part number (e.g., TPA0152PWPR).

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

BYPASS

11

Tap to voltage divider for internal mid-supply bias generator

CLK

17

I

If a 47-nF capacitor is attached, the TPA0152 generates an internal clock. An external clock can override the

internal clock input to this terminal.

DOWN

3

I

A momentary pulse on this terminal decreases the volume level by 2 dB. Holding the terminal low for a period

of time will step the amplifier through the volume levels at a rate determined by the capacitor on the CLK

terminal.

GND

1, 12

13, 24

Ground connection for circuitry. Connected to thermal pad

LHPIN

6

I

Left-channel headphone input, selected when SE/BTL is held high

LIN

10

I

Common left input for fully differential input. AC ground for single-ended inputs

LLINEIN

5

I

Left-channel line negative input, selected when SE/BTL is held low

LOUT+

4

O

Left-channel positive output in BTL mode and positive in SE mode

LOUT–

9

O

Left-channel negative output in BTL mode and high impedance in SE mode

PC-BEEP

14

I

The input for PC Beep mode. PC-BEEP is enabled when a > 1-V (peak-to-peak) square wave is input to

PC-BEEP or PCB ENABLE is high.

PVDD

7, 18

I

Power supply for output stage

RHPIN

20

I

Right channel headphone input, selected when SE/BTL is held high

RIN

8

I

Common right input for fully differential input. AC ground for single-ended inputs

RLINEIN

23

I

Right-channel line input, selected when SE/BTL is held low

ROUT+

21

O

Right-channel positive output in BTL mode and positive in SE mode

ROUT–

16

O

Right-channel negative output in BTL mode and high impedance in SE mode

SE/BTL

15

I

Input MUX control input. When this terminal is held high, the LHPIN or RHPIN and SE output is selected. When

this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected.

SHUTDOWN

22

I

When held low, this terminal places the entire device, except PC-BEEP detect circuitry, in shutdown mode.

UP

2

I

A momentary pulse on this terminal increases the volume level by 2 dB. Holding the terminal low for a period

of time will step the amplifier through the volume levels at a rate determined by the capacitor on the CLK

terminal.

VDD

19

I

Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve highest performance.