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ASM5I2304AF-2H-08-SR Datasheet(PDF) 8 Page - PulseCore Semiconductor

Part # ASM5I2304AF-2H-08-SR
Description  3.3V Zero Delay Buffer
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Manufacturer  PULSECORE [PulseCore Semiconductor]
Direct Link  http://www.onsemi.com/
Logo PULSECORE - PulseCore Semiconductor

ASM5I2304AF-2H-08-SR Datasheet(HTML) 8 Page - PulseCore Semiconductor

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November 2006
ASM5P2304A
rev 1.5
3.3V Zero Delay Buffer
8 of 14
Notice: The information in this document is subject to change without notice.
Switching Characteristics for ASM5I2304A Industrial Temperature Devices
All parameters are specified with loaded outputs
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
1/t1
Output Frequency
30pF load, -1H, -2H devices
15
133
MHz
1/t1
Output Frequency
15pF load, -1 and -2 devices
15
133
MHz
Duty Cycle
8 = (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = <66.66MHz
30pF load
40.0
50.0
60.0
%
Duty Cycle
8= (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = <50 MHz
15pF load
45.0
50.0
55.0
%
t3
Output Rise Time
8
(-1, -2)
Measured between 0.8V and 2.0V
30pF load
2.50
nS
t3
Output Rise Time
8
(-1, -2)
Measured between 0.8V and 2.0V
15pF load
1.50
nS
t3
Output Rise Time
8
(-1H, -2H)
Measured between 0.8V and 2.0V
30pF load
1.50
nS
t4
Output Fall Time
8
(-1, -2)
Measured between 2.0V and 0.8V
30pF load
2.50
nS
t4
Output Fall Time
8
(-1, -2)
Measured between 2.0V and 0.8V
15pF load
1.50
nS
t4
Output Fall Time
8
(-1H, -2H)
Measured between 2.0V and 0.8V
30pF load
1.25
nS
Output-to-output skew on same bank (-1, -2)
8
All outputs equally loaded
200
Output-to-output skew
(-1H, -2H)
All outputs equally loaded
200
Output bank A -to- output bank B skew (-1, -2H)
All outputs equally loaded
200
t5
Output bank A -to- output bank B skew (-2)
All outputs equally loaded
400
pS
t6
Delay, REF Rising Edge to FBK Rising Edge
8
Measured at VDD /2
0
±250
pS
t7
Device-to-Device Skew
8
Measured at VDD/2 on the FBK pins of the
device
0
500
pS
t8
Output Slew Rate
8
Measured between 0.8V and 2.0V using
Test Circuit #2
1
V/nS
Measured at 66.67MHz, loaded outputs,
15pF load
180
Measured at 66.67MHz, loaded outputs,
30pF load
200
tJ
Cycle-to-cycle jitter
8
(-1, -1H, -2H)
Measured at 25MHz, loaded outputs,
15pF load
100
pS
Measured at 66.67MHz, loaded outputs,
30pF load
400
tJ
Cycle-to-cycle jitter
8
(-2)
Measured at 66.67MHz, loaded outputs,
15pF load
380
pS
tLOCK
PLL Lock Time
8
Stable power supply, valid clock presented
on REF and FBK pins
1.0
mS
Note: 8. Parameter is guaranteed by design and characterization. Not 100% tested in production.


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