TPIC1502

QUAD AND HEX POWER DMOS ARRAY

SLIS054 – OCTOBER 1996

1

POST OFFICE BOX 655303

0.25

Ω Typ (Full H-Bridge)

0.4

Ω Typ (Triple Half H-Bridge)

Linear Operation

description

The TPIC1502 is a monolithic power DMOS array

that consists of ten electrically isolated N-channel

enhancement-mode power DMOS transistors,

four of which are configured as a full H-bridge and

six as a triple half H-bridge. The lower stage of the

full H-bridge is provided with an integrated

sense-FET to allow biasing of the bridge in class

A-B operation.

The TPIC1502 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation

over the case temperature range of – 40

°C to 125°C.

schematic

Q4B

GATE1A

17

OUTPUT1

19

GATE1B

21

Q2A

9

Q2B

7

5

D1

D2

GATE3A

22

OUTPUT3

1

GATE3B

4

D3

GATE4A

Q4A

OUTPUT4

GATE4B

8

GATE2A

OUTPUT2

GATE2B

Q3B

Q3A

15

11

Q1B

Q1A

GATE5A

Q5A

16

OUTPUT5

GATE5B

24

2, 12

3, 23

GND

SOURCE

VDD1

VDD2

VDD3

SENSE

20

Q2C

6

GATE2C

6 V

18

14

13

Q5B

10

NOTES: A. Terminals 3 and 23 must be externally connected.

B. Terminals 2 and 12 must be externally connected.

C. No output may be taken greater than 0.5 V below GND.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

OUTPUT3

SOURCE

GND

GATE3B

GATE2B

GATE2C

OUTPUT2

GATE4B

GATE2A

GATE5B

SOURCE

GND

GATE3A

GATE1B

SENSE

OUTPUT1

GATE4A

GATE1A

GATE5A

OUTPUT4

OUTPUT5

DW PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright

© 1996, Texas Instruments Incorporated