Electronic Components Datasheet Search |
|
P2008AG-08TT Datasheet(PDF) 3 Page - PulseCore Semiconductor |
|
P2008AG-08TT Datasheet(HTML) 3 Page - PulseCore Semiconductor |
3 / 8 page November 2006 P2008A rev 1.4 General purpose EMI Reduction IC 3 of 8 Notice: The information in this document is subject to change without notice. Spread Spectrum The Modulation Output and Spreading Selection Tables illustrate the two possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center frequency (Note: The center frequency is the frequency of the external reference input on XIN/CLKIN, Pin1). Example: The P2008A is designed for communications, digital video and imaging applications. It is not only optimized for operation in the 4MHz – 32MHz range, but its output frequency can be extended down to one half of the input clock frequency using the divide-by-two feature. This feature extends low frequency as low as to 2MHz. Setting Pin 3 low (DIV2 = 0; Divide-by-two mode) sets the output frequency (ModOUT) to half the frequency of the input clock (XIN/CLKIN). This is a simple way to generate a spread spectrum modulated low frequency clock when only a higher frequency signal is available. If you want the output frequency to be the same as the input, you can either set DIV2=1 or leave it unconnected. Selecting the P2008A’s spread options is a matter of either setting SR0=1 or SR0=0. Setting SR0=0 set as a lower modulation spread, while setting it to 1 introduces a wider spectral spread in the output clock. Refer Modulation output and Spreading Selections Tables. The example given in the figure below shows the device set to the divide-by-two mode (DIV2=0) with a lower spectrum range (SR0=0). The versatility provided by allowing both clock division and spread spectrum on one chip is already proving to be a popular solution among leading system manufacturers. P2008A Application Schematic Modulated 4.416MHz is connected to CLK input pin of the system 1 2 3 4 XIN/CLKIN XOUT DIV2 VSS SR0 5 6 7 8 SSON# Mod OUT VDD 8.832MHz Crystal +3.3V 0.1µF P2008A |
Similar Part No. - P2008AG-08TT |
|
Similar Description - P2008AG-08TT |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |