September 2006

PCS2I2310ANZ

rev 0.5

3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs

7 of 12

Notice: The information in this document is subject to change without notice.

Switching Waveforms

Duty Cycle Timing

All Outputs Rise/Fall Time

Output - Output Skew

SDRAM Buffer LH and HL Propagation Delay

Test Circuits

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

OUTPUT

OUTPUT

0.4 V

2.4 V

0.4 V

2.4 V

3.3 V

0 V

OUTPUT

OUTPUT

INPUT

GND

GND

CLKOUT

OUTPUT

TEST CIRCUIT

0.1uF

0.1uF

+3.3V

+3.3V