September 2006

PCS2I2313ANZ

rev 0.5

13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs

3 of 13

Notice: The information in this document is subject to change without notice.

Serial Configuration Map

• The Serial bits will be read by the clock driver in the

following order:

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0

• Reserved bits should be programmed to “0” or ”1”.

• Serial interface address for the PCS2I2313ANZ is:

A6

A5

A4

A3

A2

A1

A0

R/W

1

1

0

1

0

0

1

----

Byte 0: SDRAM Active/Inactive Register

(1 = Enable, 0 = Disable), Default = Enable

Bit

Pin #

Description

Bit 7

11

SDRAM5 (Active/Inactive)

Bit 6

10

SDRAM4 (Active/Inactive)

Bit 5

--

Reserved

Bit 4

--

Reserved

Bit 3

7

SDRAM3 (Active/Inactive)

Bit 2

6

SDRAM2 (Active/Inactive)

Bit 1

3

SDRAM1 (Active/Inactive)

Bit 0

2

SDRAM0 (Active/Inactive)

Byte 1: SDRAM Active/Inactive Register

(1 = Enable, 0 = Disable), Default = Enable

Bit

Pin #

Description

Bit 7

27

SDRAM11 (Active/Inactive)

Bit 6

26

SDRAM10 (Active/Inactive)

Bit 5

23

SDRAM9 (Active/Inactive)

Bit 4

22

SDRAM8 (Active/Inactive)

Bit 3

--

Reserved

Bit 2

--

Reserved

Bit 1

19

SDRAM7 (Active/Inactive)

Bit 0

18

SDRAM6 (Active/Inactive)

Byte 2: SDRAM Active/Inactive Register

(1 = Enable, 0 = Disable), Default = Enable

Bit

Pin #

Description

Bit 7

--

Reserved

Bit 6

12

SDRAM12 (Active/Inactive)

Bit 5

--

Reserved

Bit 4

--

Reserved

Bit 3

--

Reserved

Bit 2

--

Reserved

Bit 1

--

Reserved

Bit 0

--

Reserved

Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value

of all the bits is high after chip is powered up.

IIC Byte Flow

Byte

Description

1

IIC Address

2

Command (dummy value, ignored)

3

Byte Count (dummy value, ignored)

4

IIC Data Byte 0

5

IIC Data Byte 1

6

IIC Data Byte 2