September 2006

PCS2I2314ANZ

rev 0.5

14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs

6 of 13

Notice: The information in this document is subject to change without notice.

Switching Characteristics

1

Parameter

Name

Test Conditions

Min

Typ

Max

Unit

Maximum Operating Frequency

133

MHz

Duty cycle

Measured at 1.5V

45.0

50.0

55.0

%

Rising Edge Rate

3

Measured between 0.4V and

2.4V

1

2

4

V/nS

Falling Edge Rate

3

Measured between 2.4V and

0.4V

1

2

4

V/nS

Output to Output Skew

3

All outputs equally loaded

150

225

pS

SDRAM Buffer LH Prop. Delay

3

Input edge greater than 1 V/nS

1

2.7

3.5

nS

SDRAM Buffer HL Prop. Delay

3

Input edge greater than 1 V/nS

1

2.7

3.5

nS

SDRAM Buffer Enable Delay

3

Input edge greater than 1 V/nS

1

3

5

nS

SDRAM Buffer Disable Delay

3

Input edge greater than 1 V/nS

1

3

5

nS

6

Rise Time for SDATA

(Refer Test Circuit for IIC)

Refer figure no.3

250

nS

20

Fall Time for SDATA

(Refer Test Circuit for IIC)

Refer figure no.3

250

nS

Note: 1. All parameters specified with loaded outputs.

2. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/nS

3. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Test Circuit for SDRAM Enable and Disable Times

Figure 1. Load circuit for Switching times

PULSE

GENERATOR

D.U.T

500Ω

500Ω

Open

TEST

Open