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PCS2P5T907AG-48TT Datasheet(PDF) 10 Page - PulseCore Semiconductor |
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PCS2P5T907AG-48TT Datasheet(HTML) 10 Page - PulseCore Semiconductor |
10 / 21 page September 2006 PCS2P5T907A rev 0.2 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer 10 of 21 Notice: The information in this document is subject to change without notice. DC Electrical Characteristics Over Operating Range for 2.5V LVTTL 1 Symbol Parameter Test Conditions Min. Typ 8 Max Unit Input Characteristics IIH Input HIGH Current 10 VDD= 2.6V VI = VDDQ/GND ±5 IIL Input LOW Current 10 VDD= 2.6V VI = GND/VDDQ ±5 µA VIK Clamp Diode Voltage VDD= 2.4V, IIN = -18mA - 0.7 - 1.2 V VIN DC Input Voltage -0.3 +3.6 V Single-Ended Inputs 2 VIH DC Input HIGH 1.7 V VIL DC Input LOW 0.7 V Differential Inputs VDIF DC Differential Voltage 3,9 0.2 V VCM DC Common Mode Input Voltage 4,9 1150 1250 1350 mV VIH DC Input HIGH5, 6,9 VREF+ 100 mV VIL DC Input LOW5, 7,9 VREF-100 mV VREF Single-Ended Reference Voltage 5,9 1250 - mV Output Characteristics IOH= -12mA VDDQ- 0.4 V VOH Output HIGH Voltage IOH= -100µA VDDQ- 0.1 V IOL= 12mA 0.4 V VOL Output LOW Voltage IOL= 100µA 0.1 V NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and A/VREF is tied to GND. 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 5. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF. 6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 7. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient. 9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 10. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail. |
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