September 2006

PCS2I99448

rev 0.4

3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer

7 of 15

Notice: The information in this document is subject to change without notice.

APPLICATIONS INFORMATION

Timing Diagram

Figure 1. Output Clock Stop (CLK_STOP)

Driving Transmission Lines

The PCS2I99448 clock driver was designed to drive high

speed signals in a terminated transmission line

environment. To provide the optimum flexibility to the

user, the output drivers were designed to exhibit the

lowest impedance possible. With an output impedance of

series terminated transmission lines. In most high

performance clock networks, point–to–point distribution of

signals is the method of choice. In a point–to–point

scheme, either series terminated or parallel terminated

transmission lines can be used. The parallel technique

terminates the signal at the end of the line with a 50Ω

Figure 2. Single versus Dual Transmission

Lines

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the PCS2I99448 clock driver. For the series

terminated case, however, there is no DC current draw;

thus, the outputs can drive multiple series terminated

lines. Figure 2 “Single versus Dual Transmission Lines”

illustrates an output driving a single series terminated line

versus two series terminated lines in parallel. When taken

to its extreme, the fanout of the PCS2I99448 clock driver

is effectively doubled due to its capability to drive multiple

The waveform plots in Figure 3 “Single versus Dual Line

Termination Waveforms” show the simulation results of

an output driving a single line versus two lines. In both

Figure 3 . Single versus Dual Line Termination

Waveforms

cases, the drive capability of the PCS2I99448 output

buffer is more than sufficient to drive 50Ω transmission

lines on the incident edge. Note from the delay

measurements in the simulations a delta of only 43pS

exists between the two differently loaded outputs. This

suggests that the dual line driving need not be used

exclusively to maintain the tight output–to–output skew of

the PCS2I99448. The output waveform in Figure 3

“Single versus Dual Line Termination Waveforms” shows

a step in the waveform; this step is caused by the

impedance mismatch seen looking into the driver. The

parallel combination of the 33Ω series resistor plus the

output

impedance

does

not

match

the

parallel

combination of the line impedances. The voltage wave

launched down the two lines will equal:

= 1.28V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.5V. It will then increment

towards the quiescent 3.0V in steps separated by one

round trip delay (in this case 4.0nS).

Since this step is well above the threshold region it will

not cause any false clock triggering; however, designers

may be uncomfortable with unwanted reflections on the

line. To better match the impedances when driving

PCS2I99448

OUTPUT BUFFER

17Ω

PCS2I99448

OUTPUT BUFFER

17Ω

CCLK or

PCLK

CLK _ STOP

Q0 to Q11

3.0

2.5

2.0

1.5

1.0

0.5

0

24

6

8

10

12

14

TIME (nS)

In

OutA

OutB