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PCS2I5T9050AF-28TT Datasheet(PDF) 1 Page - PulseCore Semiconductor |
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PCS2I5T9050AF-28TT Datasheet(HTML) 1 Page - PulseCore Semiconductor |
1 / 10 page November 2006 PCS2P5T9050A rev 0.2 Notice: The information in this document is subject to change without notice. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com 2.5V Single Data Rate1:5 Clock Buffer Terabuffer Features • Optimized for 2.5V LVTTL • Guaranteed Low Skew < 25pS (max) • Very low duty cycle distortion< 300pS (max) • High speed propagation delay < 1.8nS. (max) • Up to 200MHz operation • Very low CMOS power levels • Hot Insert able and over-voltage tolerant inputs • 1:5 fan-out buffer • 2.5V Supply Voltage • Available in TSSOP Package Functional Description The PCS2P5T9050A 2.5V single data rate (SDR) clock buffer is a single-ended input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fan-out from a single input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. Multiple power and grounds reduce noise. Applications: PCS2P5T9050A is targeted towards Clock and signal distribution applications. Block Diagram OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL A GL G Q1 Q2 Q3 Q4 Q5 |
Similar Part No. - PCS2I5T9050AF-28TT |
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Similar Description - PCS2I5T9050AF-28TT |
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