November 2006

PCS5I961C

rev 0.3

Low Voltage Zero Delay Buffer

8 of 14

Notice: The information in this document is subject to change without notice.

Due to the statistical nature of I/O jitter a rms value (1

σ) is

specified. I/O jitter numbers for other confidence factors

(CF) can be derived from Table 8.

CF

Probability of clock edge within the

distribution

± 1σ

0.68268948

± 2σ

0.95449988

± 3σ

0.99730007

± 4σ

0.99993663

± 5σ

0.99999943

± 6σ

0.99999999

The feedback trace delay is determined by the board

layout and can be used to fine-tune the effective delay

through each device. In the following example calculation

a I/O jitter confidence factor of 99.7% (± 3 σ) is assumed,

resulting in a worst case timing uncertainty from input to

any output of -275 pS to 315 pS relative to CCLK:

Due to the frequency dependence of the I/O jitter, Figure

8. “Max. I/O Jitter versus frequency” can be used for a

more precise timing performance analysis.

Figure 8. Max. I/O Jitter versus frequency

Power Consumption of the PCS5I961C and Thermal

Management

The PCS5I961C AC specification is guaranteed for the

entire operating frequency range up to 200MHz. The

PCS5I961C power consumption and the associated long-

term reliability may decrease the maximum frequency

limit, depending on operating conditions such as clock

frequency, supply voltage, output loading, ambient

temperature, vertical convection and thermal conductivity

of package and board. This section describes the impact

of these parameters on the junction temperature and

gives a guideline to estimate the PCS5I961C die junction

temperature and the associated device reliability.

Table 9: Die junction temperature and MTBF

Junction temperature (°C)

MTBF (Years)

100

20.4

110

9.1

120

4.2

130

2.0

Increased power consumption will increase the die

junction temperature and impact the device reliability

(MTBF). According to the system-defined tolerable

MTBF, the die junction temperature of the PCS5I961C

needs to be controlled and the thermal impedance of the

board/package

should

be

optimized.

The

power

dissipated in the PCS5I961C is represented in equation

PCS5I961C, CPD is the power dissipation capacitance

output load, N is the number of active outputs (N is

always 27 in case of the PCS5I961C). The PCS5I961C

supports driving transmission lines to maintain high signal

integrity and tight timing parameters. Any transmission

line will hide the lumped capacitive load at the end of the

transmission line systems and can be eliminated from

equation 1. Using parallel termination output termination

results in equation 2 for power dissipation. In equation 2,

P stands for the number of outputs with a parallel or

zero in equation 2 and can be eliminated. In general, the

use of controlled transmission line techniques eliminates

the impact of the lumped capacitive loads at the end lines

and greatly reduces the power dissipation of the device.

function of the power consumption.

0

50

70

90

110

130

190

Clock frequency [MHz]

2

10

12

14

16

18

F_RANGE=1

8

6

4

170

150

F_RANGE=0