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PCS5I9351G-32-LT Datasheet(PDF) 5 Page - PulseCore Semiconductor |
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PCS5I9351G-32-LT Datasheet(HTML) 5 Page - PulseCore Semiconductor |
5 / 13 page November 2006 PCS5I9351 rev 0.3 2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer 5 of 13 Notice: The information in this document is subject to change without notice. DC Electrical Specifications (V DD = 2.5V ± 5%, TA = -40°C to +85°C) Parameter Description Condition Min Typ Max Unit VIL Input Voltage, Low LVCMOS 0.7 V VIH Input Voltage, High LVCMOS 1.7 VDD+0.3 V VPP Peak-Peak Input Voltage LVPECL 250 1000 mV VCMR Common Mode Range 1 LVPECL 1.0 VDD- 0.6 V VOL Output Voltage, Low 2 IOL= 15mA - 0.6 V VOH Output Voltage, High 2 IOH= –15mA 1.8 V IIL Input Current, Low 3 VIL= VSS -100 µA IIH Input Current, High 3 VIL= VDD 100 µA IDDA PLL Supply Current AVDD only 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD 7 mA Outputs loaded @ 100 MHz 180 IDD Dynamic Supply Current Outputs loaded @ 200 MHz 210 mA CIN Input Pin Capacitance 4 pF ZOUT Output Impedance 14 18 22 Ω Note: 1 VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 2.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated transmission lines. 3.Inputs have pull-up or pull-down resistors that affect the input current. DC Electrical Specifications (V DD = 3.3V ± 5%, TA = -40°C to +85°C) Parameter Description Condition Min Typ Max Unit VIL Input Voltage, Low LVCMOS 0.8 V VIH Input Voltage, High LVCMOS 2.0 VDD+0.3 V VPP Peak-Peak Input Voltage LVPECL 250 1000 mV VCMR Common Mode Range 1 LVPECL 1.0 VDD– 0.6 V IOL= 24 mA 0.55 VOL Output Voltage, Low 2 IOL= 12 mA 0.30 V VOH Output Voltage, High 2 IOH= –24 mA 2.4 V IIL Input Current, Low 3 VIL= VSS –100 µA IIH Input Current, High 3 VIL= VDD 100 µA IDDA PLL Supply Current AVDD only 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD 7 mA Outputs loaded @ 100 MHz 270 IDD Dynamic Supply Current Outputs loaded @ 200 MHz 300 mA CIN Input Pin Capacitance 4 pF ZOUT Output Impedance 12 15 18 Ω Note: 1 VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 2.Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated transmission lines. 3.Inputs have pull-up or pull-down resistors that affect the input current. |
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