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PCS5I9653A Datasheet(PDF) 5 Page - PulseCore Semiconductor |
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PCS5I9653A Datasheet(HTML) 5 Page - PulseCore Semiconductor |
5 / 13 page November 2006 PCS5I9653A rev 0.3 3.3V 1:8 LVCMOS PLL Clock Generator 5 of 13 Notice: The information in this document is subject to change without notice. Table 6: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = -40°C to +85°C)6 Symbol Characteristics Min Typ Max Unit Condition fREF Input reference frequency ÷4 feedback 7 PLL mode, external feedback ÷8 feedback 8 Input reference frequency in PLL bypass mode 9 50 25 0 125 62.5 200 MHz MHz MHz PLL locked PLL locked fVCO VCO operating frequency range 10,11 200 500 MHz fVCOlock VCO lock frequency range 12 145 500 MHz fMAX Output Frequency ÷4 feedback 8 ÷8 feedback 9 50 25 125 62.5 MHz MHz PLL locked PLL locked VPP Peak-to-peak input voltage PCLK 450 1000 mV LVPECL VCMR 13 Common Mode Range PCLK 1.2 VCC-0.75 V LEPVCL tPW,MIN Input Reference Pulse Width 14 2 nS t( Ø) Propagation Delay (static phase offset) 15 PCLK to FB_IN -75 125 pS PLL locked tPD Propagation Delay PLL and divider bypass (BYPASS=0), PCLK to Q0-7 PLL disable (BYPASS=1 and PLL_EN=0), PCLK to Q0-7 1.2 3.0 3.3 7.0 nS nS tsk(O) Output-to-output Skew 16 150 pS tsk(PP) Device-to-device Skew in PLL and divider bypass 17 1.5 nS BYPASS=0 DC Output duty cycle 45 50 55 % PLL locked tR,tF Output Rise/Fall Time 0.1 1.0 nS 0.55 to 2.4V tPLZ, HZ Output Disable Time 7.0 nS tPZL, LZ Output Enable Time 6.0 nS tJIT(CC) Cycle-to-cycle jitter 100 pS tJIT(PER) Period Jitter 100 pS tJIT( Ø) I/O Phase Jitter 18 RMS (1 σ) 25 pS BW PLL closed loop bandwidth 19 ÷ 4 feedback 8 PLL mode, external feedback ÷8 feedback 9 0.8-4 0.5 -1.3 MHz tLOCK Maximum PLL Lock Time 10 mS 6 AC characteristics apply for parallel output termination of 50Ω to VTT. 7 ÷4 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0. 8 ÷8 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0. 9 In bypass mode, the PCS3P9653A divides the input reference clock. 10 The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB. 11 fVCO is frequency range where AC parameters are guaranteed. 12 fVCOlock is frequency range that the PLL guaranteed to lock, AC parameters only guaranteed over fVCO. 13 VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t( Ø ). 14 Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN . fREF . 100% and DCREF,MAX = 100% - DCREF,MIN. E.g. at fREF=100 MHz the input duty cycle range is 20% < DC < 80%. 15 Valid for fREF=50 MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t( Ø ) [ps] = 50 ps ± (1÷(120 . fREF)). 16 See application section for part-to-part skew calculation in PLL zero-delay mode. 17 For a specified temperature and voltage, includes output skew. 18 I/O phase jitter is reference frequency dependent. See application section for details. 19 -3 dB point of PLL transfer characteristics. |
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