November 2006

PCS5I9658

rev 0.3

3.3V 1:10 LVCMOS PLL Clock Generator

7 of 15

Notice: The information in this document is subject to change without notice.

Applications Information

Driving Transmission Lines

The PCS5I9658 supports output clock frequencies from

50

to

250MHz.

Two

different

feedback

divider

configurations can be used to achieve the desired

frequency operation range. The feedback divider

(VCO_SEL) should be used to situate the VCO in the

frequency lock range between 200 and 500MHz

for

stable and optimal operation. Two operating frequency

ranges are supported: 50 to 125MHz and 100 to 250

MHz. Table 7 illustrates the configurations supported by

the PCS5I9658. PLL zero-delay is supported

if

BYPASS=1, PLL_EN=1 and the input frequency is within

the specified PLL reference frequency range.

Table 7: PCS5I9658 Configurations (QFB connected to FB_IN)

Frequency

BYPASS

PLL_

EN

VCO_

SEL

Operation

Ratio

Output range (fQ0-7)

VCO

0

X

X

Test mode: PLL and divider bypass

0-250MHz

n/a

1

0

0

Test mode: PLL bypass

0-125MHz

n/a

1

0

1

Test mode: PLL bypass

0-62.5MHz

n/a

1

1

0

PLL mode (high frequency range)

100 to 250MHz

1

1

1

PLL mode (low frequency range)

50 to 125MHz

Power Supply Filtering

The PCS5I9658 is a mixed analog/digital product. Its

analog circuitry is naturally susceptible to random noise,

especially if this noise is seen on the power supply pins.

device characteristics, for instance I/O jitter. The

PCS5I9658 provides separate power supplies for the

of the device. The purpose of this design technique is to

isolate the high switching noise digital outputs from the

relatively sensitive internal analog phase-locked loop. In a

digital system environment where it is more difficult to

minimize noise on the power supplies a second level of

isolation may be required. The simple but effective form

the PCS5I9658. Figure 3. illustrates a typical power

supply filter scheme. The PCS5I9658 frequency and

phase stability is most susceptible to noise with spectral

content in the 100KHz to 20MHz range. Therefore the

filter should be designed to target this range. The key

parameter that needs to be met in the final filter design is

(20 mA maximum), assuming that a minimum of 2.835V

defined by the required filter characteristics: the RC filter

should provide attenuation greater than 40 dB for

noise whose spectral content is above 100KHz. In the

Supply Filter”, the filter cut-off frequency is around

3-5KHz and the noise attenuation at 100KHz is better

than 42dB.

As the noise frequency crosses the series resonant point

of an individual capacitor its overall impedance begins to

look inductive and thus increases with increasing

frequency. The parallel capacitor combination shown

ensures that a low impedance path to ground exists for

frequencies well above the bandwidth of the PLL.

Although the PCS5I9658 has several design features to

minimize the susceptibility to power supply noise

(isolated power and grounds and fully differential PLL)

there still may be applications in which overall

performance is being degraded due to system power

supply noise. The power supply filter schemes discussed

PCS5I9658

VCC_PLL

10 nF

33…100 nF

µF