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PCS5I9774 Datasheet(PDF) 8 Page - PulseCore Semiconductor |
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PCS5I9774 Datasheet(HTML) 8 Page - PulseCore Semiconductor |
8 / 12 page September 2006 PCS5I9774 rev 0.4 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer 8 of 12 Notice: The information in this document is subject to change without notice. AC Electrical Specifications (VDD = 3.3V ± 5%, T A = -40°C to +85°C) 1 Parameter Description Condition Min Typ Max Unit fVCO VCO Frequency 200 500 MHz ÷8 Feedback 25 62.5 ÷12 Feedback 16.6 41.6 ÷16 Feedback 12.5 31.25 ÷24 Feedback 8.3 20.8 ÷32 Feedback 6.25 15.625 ÷48 Feedback 4.2 10.4 fin Input Frequency Bypass mode (PLL_EN = 0) 0 200 MHz frefDC Input Duty Cycle 25 75 % tr, tf TCLK Input Rise/FallTime 0.8V to 2.0V 1.0 nS ÷4 Output 50 125 ÷8 Output 25 62.5 ÷12 Output 16.6 41.6 ÷16 Output 12.5 31.25 fMAX Maximum Output Frequency ÷24 Output 8.3 20.8 MHz DC Output Duty Cycle 45 55 % tr, tf Output Rise/Fall times 0.8V to 2.4V 0.1 1.0 nS t(φ) Propagation Delay (static phase offset) TCLK to FB_IN, same VDD, does not include jitter -100 100 pS tsk(O) Output-to-Output Skew Skew within Bank 150 pS Banks at same voltage, same frequency 150 Banks at same voltage, different frequency 225 tsk(B) Bank-to-Bank Skew Banks at different voltage 250 pS tPLZ, HZ Output Disable Time 10 nS tPZL, ZH Output Enable Time 10 nS BW PLL Closed Loop Bandwidth (–3dB) 0.5 - 1.0 MHz Same frequency 150 tJIT(CC) Cycle-to-Cycle Jitter Multiple frequencies 300 pS tJIT(PER) Period Jitter 100 pS tJIT(φ) I/O Phase Jitter I/O at same VDD 150 pS tLOCK Maximum PLL Lock Time 1 mS Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. |
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Similar Description - PCS5I9774 |
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