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PCS812MIUKF Datasheet(PDF) 3 Page - PulseCore Semiconductor |
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PCS812MIUKF Datasheet(HTML) 3 Page - PulseCore Semiconductor |
3 / 8 page January 2007 PCS811/PCS812 rev 0.1 5-Pin µP Voltage Supervisor with Manual Reset 3 of 8 Notice: The information in this document is subject to change without notice. DETAIL DESCRIPTION RESET OUTPUT µP will be activated at a valid reset state. These µP supervisory circuits assert reset to prevent code execution errors during power-up, power-down, or brownout conditions. RESET is guaranteed to be a logic low for V TH>VCC>0.9V. Once VCC exceeds the reset threshold, an internal timer keeps RESET low for the reset timeout period; after this interval, RESET goes high. If a brownout condition occurs (VCC drops below the reset threshold), RESET goes low. Any time VCC goes below the reset threshold, the internal timer resets to zero, and RESET goes low. The internal timer is activated after VCC returns above the reset threshold, and RESET remains low for the reset timeout period. The manual reset input (MR) can also initiate a reset. PCS812 has an active-high RESET output that is the inverse of PCS811’s RESET output.PCS811’s RESET output. MANUAL RESET INPUT Many µP-based products require manual reset capability, allowing operators, test technicians, or external logic circuitry to initiate a reset. Logic low on MR asserts reset. Reset will remain asserted for the Reset Active Timeout Period (tRP) after MR returns high. This input has an internal 20KΩ pull-up resistor, so it can be floating if it is not used. MR can be driven with TTL or CMOS-logic levels, or with open-drain/collector outputs. Another alternative is to connect a normal switch from MR to GND to create a manual reset function. Connecting a 0.1µF capacitor from MR to ground can provide noise immunity to prevent noise caused by long cables of MR or noisy environment. BENEFITS OF HIGHLY ACCURATE RESET THRESHOLD PCS811/812 with specified voltage as 5V±10% or 3V±10% are ideal for systems using a 5V±5% or 3V±5% power supply. The reset is guaranteed to assert after the power supply falls out of regulation, but before power drops below the minimum specified operating voltage range of the system ICs. The pre-trimmed thresholds are reducing the range over which an undesirable reset may occur. APPLICATION INFORMATION NEGATIVE-GOING VCC TRANSIENTS In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, PCS811 series are relatively resistant to short-duration negative-going VCC transient. ENSURING A VALID RESET OUTPUT DOWN TO VCC=0 When VCC falls below 0.9V, PCS811 RESET output no longer sinks current; it becomes an open circuit. In this case, high-impedance CMOS logic inputs connecting to RESET can drift to undetermined voltages. Therefore, PCS811/812 with CMOS is perfect for most applications of VCC below 0.9V. However in applications where RESET must be valid down to 0V, adding a pull-down resistor to RESET causes any leakage currents to flow to ground, holding RESET low. INTERFACING TO µP WITH BIDIRECTIONAL RESET PINS µPs with bidirectional reset pins can contend with PCS811/812 reset outputs. If PCS811 RESET output is asserted high and the µP wants to pull it low, indeterminate logic levels may occur. To correct such cases, connect a resistor between PCS811 RESET (or PCS812 RESET) output and the µP reset I/O. Buffer the reset output to other system components. |
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