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STM8S207R8 Datasheet(PDF) 5 Page - STMicroelectronics |
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STM8S207R8 Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 8 page Errata sheet Silicon limitations 5/8 2.4 UART PE flag cannot be cleared during reception of first half of Stop bit Description When the UART is in reception mode and a parity error (PE) occurs, the PE flag is set by hardware. This flag cannot be cleared during the first half of the Stop bit period. If software tries to clear the PE flag at this time, the flag is set again by hardware, generating an unwanted interrrupt if the PIEN bit is set in the UART_CR1 register. Workaround Disable PE interrupts and, after the RXNE bit is set, use polling to manage the PE flag. For example, this could be done in the RXNE interrupt service routine. |
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