TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15

TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30

ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS

SLVS227 – AUGUST 1999

8

POST OFFICE BOX 655303

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

At VDD

VIH = VIT– + 0.2 V,

VIL = VIT– – 0,2 V

6

tw

Pulse width

At MR

VDD ≥ VIT +0 2 V

VIL = 0 3xVDD

VIH =0 7×VDD

1

µs

At WDI

VDD ≥ VIT– + 0.2 V,

VIL = 0.3xVDD,

VIH = 0.7×VDD

0.1

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ttout

Watchdog time out

VDD ≥ VIT– + 0.2 V,

See timing diagram

0.8

1.4

2.1

s

td

Delay time

VDD > VIT–+ 0.2 V,

See timing diagram

100

180

260

ms

tPHL

Propagation delay time, high-to-low-level output

MR to RESET delay

(TPS3123/25 only)

VDD ≥ VIT– + 0.2 V,

VIL 02 × VDD

0.1

µs

tPLH

Propagation delay time, low-to-high-level output

MR to RESET delay

(TPS3125 only)

VIL = 0.2 × VDD,

VIH = 0.8 × VDD

0.1

µs

tPHL

Propagation delay time, high-to-low-level output

VDD to RESET delay

VIL =VIT

02 V

10

tPLH

Propagation delay time, low-to-high-level output

VDD to RESET delay

(TPS3124/25 only)

VIL = VIT– – 0.2 V,

VIH = VIT– + 0.2 V

10

µs