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PO74G74ASiR Datasheet(PDF) 1 Page - Potato Semiconductor Corporation |
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PO74G74ASiR Datasheet(HTML) 1 Page - Potato Semiconductor Corporation |
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1 / 6 page  Copyright © Potato Semiconductor Corporation 54, 74 Series GHz Logic PO54G74A, PO74G74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 10/10/07 1 FEATURES: Pin Configuration Pin Description 1 2 3 4 5 6 7 14 13 12 11 10 9 8 DESCRIPTION: Potato Semiconductor’s PO74G74A is designed for world top performance using submicron CMOS technology to achieve higher than 600MHz TTL /CMOS output frequency with less than 2ns propaga- tion delay. This dual D flip-flop is designed for 1.65-V to 3.6-V VCC operation. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment. 1CLR 1D 1CLK 1PRE 1Q 1Q GND VCC 2CLR 2D 2CLK 2PRE 2Q 2Q INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H H H H ↑ H H L H H ↑ L L H H H L X Q0 Q 0 . Patented technology . Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C . Operating frequency is faster than 600MHz . VCC Operates from 1.65V to 3.6V . Propagation delay < 2ns max with 15pf load . Low input capacitance: 4pf typical . Latch-Up Performance Exceeds 250 mA Per JESD 17 . ESD Protection Exceeds JESD 22 . 5000-VHuman-BodyModel (A114-A) . 200-VMachineModel (A115-A) . Available in 14pin 150mil wide SOIC package . Available in 14pin Ceramic Dual Flatpack . Available in 20pin Leadless Ceramic Chip Carrier Logic Block Diagram 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1CLR 1 2 1CLR 1PRE 1D D D Q Q Q Q 1Q 2Q 2Q 2PRE PRE PRE CLR CLR 2CLK 2CLR Vcc 2D 1Q GND 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 2D NC 2CLK NC 2PRE 1CLK NC 1PRE NC 1Q |
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