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PO100HSTL180ASR Datasheet(PDF) 1 Page - Potato Semiconductor Corporation |
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PO100HSTL180ASR Datasheet(HTML) 1 Page - Potato Semiconductor Corporation |
1 / 8 page Copyright © Potato Semiconductor Corporation Differential LVDS/LVPECL/HSTL to LVTTL Translator PO100HSTL180A 04/26/09 1 FEATURES: Pin Configuration Logic Block Diagram Pin Description DESCRIPTION: Potato Semiconductor’s PO100HSTL180A is designed for world top performance using submicron CMOS technology to achieve 1GHz LVTTL output frequency with less than 1.8ns propagation delay and 1.65GHz HSTL output frequency with less than 1.4ns propagation delay. The PO100HSTL180A is a low-skew, The small outline 14 pin package and the low skew design to make it ideal for applications which require the translation of a clock or a data signal. • Patented Technology • Differential LVDS/LVPECL/HSTL to LVTTL Translator - Operating frequency up to 1GHz with 2pf load - Operating frequency up to 800MHz with 5pf load - Operating frequency up to 450MHz with 15pf load - Very low output pin to pin skew < 150ps - Propagation delay < 1.8ns max with 15pf load • LVTTL/LVCMOS to Differential HSTL Translator - Operating frequency up to 1.65GHz with 5pf load - Operating frequency up to 500MHz with 15pf load - Very low output pin to pin skew < 100ps - Propagation delay < 1.4ns max with 15pf load • 2.4V to 3.6V power supply • Industrial temperature range: –40°C to 85°C • Available in 14-pin 150ml SOIC package LVTTL/LVCMOS to Differential HSTL Translator RECEIVER INPUTS RECEIVER OUTPUT VID = VA– VB RE R VID ≥ 10 mV L H 10 mV < VID < 10 mV L ? VID ≤ –10 mV L L Open L H X H Z DRIVER INPUTS DRIVER OUTPUTS D DE Y Z L H L H H H H L Open H L H X L Z Z 1 2 3 4 5 6 7 14 13 12 11 10 9 8 NC R RE DE D GND GND VCC VCC A B Z Y NC R D Y Z A B DE RE 2 5 4 3 9 10 12 11 |
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