TPS70745, TPS70748, TPS70751, TPS70758, TPS70702

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS

WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS

SLVS291 – MAY 2000

4

POST OFFICE BOX 655303

detailed block diagram – adjustable voltage version

UVLO

Thermal

Shutdown

Shutdown

2.5 V

+

–

Current

Sense

Reference

VREF

VREF

ENA_1

ENA_1

Rising Edge

Deglitch

0.95

× VREF

FB2

Falling Edge

Delay

VIN1

0.95

× VREF

FB1

Rising Edge

Deglitch

Falling Edge

Deglitch

0.83

× VREF

FB2

UV Comp

Falling Edge

Deglitch

0.83

× VREF

FB1

UV Comp

Power

Sequence

Logic

SHUTDOWN

ENA_1

ENA_2

VIN1

Current

Sense

+

–

ENA_2

ENA_2

VREF

VIN1 (2 Pins)

GND

EN

SEQ

(see Note B)

VIN2 (2 Pins)

VOUT1 (2 Pins)

FB1

(see Note A)

PG1

MR2

RESET

MR1

FB2

(see Note A)

VOUT2 (2 Pins)

VIN1

NOTES: A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device.

For other implementations, refer to FB terminals connection discussion in the application information section.

B. If the SEQ terminal is floating at the input, VOUT2 will power up first.