TPS77901, TPS77918, TPS77925, TPS77930

250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

4

POST OFFICE BOX 655303

TPS779xx RESET timing diagram

† Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards

for semiconductor symbology.

VI

Vres†

Vres

t

t

t

VO

Threshold

Voltage

RESET

Output

220 ms

Delay

220 ms

Delay

Output

Undefined

Output

Undefined

VIT +‡

VIT –‡

VIT –‡

VIT +‡

‡ VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT–

to VIT+ is the hysteresis voltage.