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TPS77401DGK Datasheet(PDF) 6 Page - Texas Instruments |
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TPS77401DGK Datasheet(HTML) 6 Page - Texas Instruments |
6 / 23 page TPS77301, TPS77318, TPS77327, TPS77328, TPS77333 WITH RESET OUTPUT TPS77401, TPS77418, TPS77427, TPS77428, TPS77433 WITH POWER GOOD OUTPUT 250-mA LDO REGULATORS WITH INTEGRATED RESET OR PG SLVS281A – FEBRUARY 2000 – REVISED MARCH 2000 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS774xx PG timing diagram † Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. VI Vres† Vres t t t VO Threshold Voltage PG Output Output Undefined Output Undefined VIT +‡ VIT –‡ VIT –‡ VIT +‡ ‡ VIT –Trip voltage is typically 18% lower than the output voltage (82%VO) VIT– to VIT+ is the hysteresis voltage. |
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