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SN75DP139RGZT Datasheet(PDF) 8 Page - Texas Instruments |
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SN75DP139RGZT Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 32 page  SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com Table 1. Control Pin Lookup Table SIGNAL LEVEL(1) STATE DESCRIPTION OE_N H Power Saving Main Link is disabled. IN_Dx termination = 50 Ω with common mode voltage set to Mode 0V. OUT_Dx outputs = high impedance L Normal Mode IN_Dx termination = 50 Ω OUT_Dx outputs = active I2C_EN H HDMI The Internal I2C register is active and readable when the TMDS port is selected indicating that the connector being used is HDMI. This mode selects the fastest rise and fall time for the TMDS differential output signals L DVI The Internal I2C register is disabled and not readable when the TMDS port is selected indicating that the connector being used is DVI. This mode selects a slower rise and fall time for the TMDS differential output signals See DVI Application Section. VSadj 4.02 k Ω Output Voltage Driver output voltage swing precision control to aid with system compliance ±5% Swing Contol HPDINV H HPD Inversion HPD_SOURCE VOH =0.9V (typical) and HPD logic is inverted L HPD HPD_SOURCE VOH =3.2V (typical) and HPD logic is non-inverted non-inversion SRC H Edge Rate: SRC helps to slow down the rise and fall time. SRC =High adds ~60ps to the rise Slowest and fall time of the TMDS differential output signals in addition to the I2C_EN pin selection L Edge Rate: Slow SRC helps to slow down the rise and fall time. SRC =Low adds ~30ps to the rise and fall time of the TMDS differential output signals in addition to the I2C_EN pin selection Hi-Z Edge Rate Leaving the SRC pin High Z, will keep the default rise and fall time of the TMDS differential output signals as selected by the I2C_EN pin. It is recommended that an external resistor-divider (less than 100 k Ω) is used so that voltage on this pin = VCC/2, if Hi-Z logic level is intended on this pin. OVS H Offset 1 DDC source side VOL and VIL offset range 1 L Offset 2 DDC source side VOL and VIL offset range 2 Hi-Z Offset 3 DDC source side VOL and VIL offset range 3 It is recommended that an external resistor-divider (less than 100 k Ω) is used so that voltage on this pin = VCC/2, if Hi-Z logic level is intended on this pin. DDC_EN H DDC Buffer DDC Buffer is enabled enabled L DDC buffer DDC Buffer is disabled disabled (1) (H) Logic High; (L) Logic Low; (Z) High Z 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 |
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