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TMX320C6742ZWT3 Datasheet(PDF) 4 Page - Texas Instruments |
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TMX320C6742ZWT3 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 167 page  1.3 Description TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com The device is a Low-power applications processor based on a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 64KB memory space that is shared between program and data space. L2 also has a 1024KB Boot ROM. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system. The peripheral set includes: one inter-integrated circuit (I2C) Bus interface; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; one multichannel buffered serial port (McBSP) with FIFO buffers; one SPI interface with multiple chip selects; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; one UART interface ( with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The device has a complete set of development tools for the DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution. TMS320C6742 Fixed/Floating-Point DSP 4 Submit Documentation Feedback |
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