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TVP3026M Datasheet(PDF) 11 Page - Texas Instruments |
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TVP3026M Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 95 page  Military Extension M Revision 1–5 1.4 Ordering Information TVP3026 – XXX – X AXXX Pixel Clock Frequency Indicator Must contain three characters: – 175: 175-MHz pixel clock Package Must contain three letters: HFG: Ceramic, Quad Flat Pack 1.5 Terminal Functions† TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AVDD 82, 86, 88, 89 Analog power. All AVDD terminals must be connected. A separate cutout in the DVDD plane should be made for AVDD. The DVDD and AVDD planes should be connected only at a single point through a ferrite bead close to where power enters the board. CLK0 109 I Dot clock 0 TTL input. CLK0 can be selected to drive the dot clock at frequencies up to 140 MHz. When using the VGA port, the maximum frequency is 85 MHz. CLK0 can be selected as the latch clock for VGA data and video controls. (power-up default). CLK1 110 I Dot clock 1 TTL input. CLK1 can be selected to drive the dot clock at frequencies up to 140 MHz. CLK2, CLK2 111, 112 I Dual-mode dot clock input. These inputs are ECL-compatible inputs. Alternatively, CLK2 and CLK2 may be used as individual TTL clock inputs. Programming the clock selection register selects the chosen configuration. These inputs may be selected as the dot clock up to the device limit while in the ECL mode or up to 140 MHz in the TTL mode. COMP1, COMP2 79, 81 I Compensation. COMP1 and COMP2 provide compensation for the internal reference amplifier. A 0.1- µF ceramic capacitor is required between COMP1 and COMP2. This capacitor must be as close to the device as possible to avoid noise pick up. DVDD 2, 18, 40, 41, 46, 67, 120, 140 Digital power. All DVDD terminals must be connected to the digital power plane with sufficient decoupling capacitors near the TVP3026. D7 – D0 48 – 55 I/O MPU interface data bus. These terminals are used to transfer data in and out of the register map, palette RAM, and cursor RAM. FS ADJUST 78 I Full-scale adjustment. A resistor connected between this terminal and ground controls the full-scale range of the DACs. GND 17, 42, 47, 68, 71, 73, 75, 77, 83–85, 87, 121, 139, 163 Ground. All GND terminals must be connected. A common ground plane should be used. † All unused inputs should be tied to a logic level and not be allowed to float. |
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