UC2843 datasheet(6/8 Pages) TI | Current Mode PWM Controller

6 page

High peak currents associated with capacitive loads necessi-

tate careful grounding techniques. Timing and bypass capaci-

tors should be connected close to pin 5 in a single point

ground. The transistor and 5k potentiometer are used to sam-

ple the oscillator waveform and apply an adjustable ramp to

pin 3.

Shutdown of the UC1842 can be accomplished by two meth-

ods; either raise pin 3 above 1V or pull pin 1 below a voltage

two diode drops above ground. Either method causes the out-

put of the PWM comparator to be high (refer to block diagram).

The PWM latch is reset dominant so that the output will remain

low until the next clock cycle after the shutdown condition at

pin 1 and/or 3 is removed. In one example, an externally

latched shutdown may be accomplished by adding an SCR

which will be reset by cycling VCC below the lower UVLO

threshold. At this point the reference turns off, allowing the

SCR to reset.

UC1842/3/4/5

UC2842/3/4/5

UC3842/3/4/5

OUTPUT SATURATION CHARACTERISTICS

ERROR AMPLIFIER OPEN-LOOP

FREQUENCY RESPONSE

OPEN-LOOP LABORATORY FIXTURE

SHUT DOWN TECHNIQUES

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